/******************************************************************************
* Copyright (C) 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _XILSKEY_CONFIG_H
#define _XILSKEY_CONFIG_H

#include "xilskey_utils.h"

/* #undef XPAR_XSK_ARM_PLATFORM */
/* #undef XPAR_XSK_MICROBLAZE_PLATFORM */
/* #undef XPAR_XSK_MICROBLAZE_ULTRA_PLUS */
/* #undef XPAR_XSK_MICROBLAZE_ULTRA */
#define XSK_USER_DEVICE_SERIES		XSK_FPGA_SERIES_ZYNQ
/* #undef XSK_USER_DEVICE_ID */
/* #undef XSK_USER_DEVICE_IRLEN */
#define XSK_USER_DEVICE_NUMSLR		1

#endif /* XILSKEY_CONFIG_H */
