<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2026.1 (64-bit)                              -->
<!-- SW Build 6504319 on Tue Jun 09 04:59:37 MDT 2026                  -->
<!--                                                                         -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
<!-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.   -->
<!-- Jun  9 2026                                                             -->
<!--                                                                             -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file.                                                      -->

<MemInfo Version="1" Minor="9">
  <Processor Endianness="Little" InstPath="zynq7000_preset_i/processing_system7_0">
    <AddressSpace Name="zynq7000_preset_i_processing_system7_0.zynq7000_preset_i_axi_bram_ctrl_0" Begin="1073741824" End="1073750015">
      <AddressSpaceRange Name="zynq7000_preset_i_processing_system7_0.zynq7000_preset_i_axi_bram_ctrl_0" Begin="1073741824" End="1073750015" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
        <BusBlock>
          <BitLane MemType="RAMB36" Placement="X3Y58" Read_Width="0" SLR_INDEX="-1">
            <DataWidth MSB="15" LSB="0"/>
            <AddressRange Begin="0" End="2047"/>
            <BitLayout pattern=""/>
            <Parity ON="false" NumBits="0"/>
          </BitLane>
          <BitLane MemType="RAMB36" Placement="X3Y57" Read_Width="0" SLR_INDEX="-1">
            <DataWidth MSB="31" LSB="16"/>
            <AddressRange Begin="0" End="2047"/>
            <BitLayout pattern=""/>
            <Parity ON="false" NumBits="0"/>
          </BitLane>
        </BusBlock>
      </AddressSpaceRange>
    </AddressSpace>
  </Processor>
  <Config>
    <Option Name="Part" Val="xc7z045ffg900-2"/>
  </Config>
  <DRC>
    <Rule Name="RDADDRCHANGE" Val="false"/>
  </DRC>
</MemInfo>
