// SPDX-License-Identifier: GPL-2.0
/*
 * dts file for Xilinx Versal with PM
 *
 * (C) Copyright 2017-2022 Xilinx, Inc.
 * (C) Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
 *
 * Michal Simek <michal.simek@amd.com>
 */

#include "include/dt-bindings/power/xlnx-versal-power.h"
#include "include/dt-bindings/power/xlnx-versal-regnode.h"
#include "include/dt-bindings/clock/xlnx-versal-clk.h"
#include "include/dt-bindings/reset/xlnx-versal-resets.h"

/ {
	pl_alt_ref: pl-alt-ref {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
		clock-output-names = "pl_alt_ref_clk";
	};

	ref: ref {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
		clock-output-names = "ref_clk";
	};

	rtc_clk: rtc-clk {
		bootph-all;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "rtc_clk";
	};

	can0_clk: can0-clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&versal_clk CAN0_REF>;
		clock-div = <2>;
		clock-mult = <1>;
		clock-output-names = "can0_clk";
	};

	can1_clk: can1-clk {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clocks = <&versal_clk CAN1_REF>;
		clock-div = <2>;
		clock-mult = <1>;
		clock-output-names = "can1_clk";
	};

	firmware {
		versal_firmware: versal-firmware {
			compatible = "xlnx,versal-firmware";
			interrupt-parent = <&imux>;
			bootph-all;
			method = "smc";
			#power-domain-cells = <1>;

			versal_clk: clock-controller {
				bootph-all;
				#clock-cells = <1>;
				compatible = "xlnx,versal-clk";
				clocks = <&ref>, <&pl_alt_ref>;
				clock-names = "ref", "pl_alt_ref";
			};

			zynqmp_power: power-management {
				compatible = "xlnx,zynqmp-power";
			};

			versal_reset: reset-controller {
				compatible = "xlnx,versal-reset";
				#reset-cells = <1>;
			};

			pinctrl0: pinctrl {
				compatible = "xlnx,versal-pinctrl";
			};

			versal_sec_cfg: versal-sec-cfg {
				compatible = "xlnx,versal-sec-cfg";
				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					bbram_zeroize: bbram-zeroize@4 {
						reg = <0x04 0x4>;
					};

					bbram_key: bbram-key@10 {
						reg = <0x10 0x20>;
					};

					bbram_usr: bbram-usr@30 {
						reg = <0x30 0x4>;
					};

					bbram_lock: bbram-lock@48 {
						reg = <0x48 0x4>;
					};

					user_key0: user-key@110 {
						reg = <0x110 0x20>;
					};

					user_key1: user-key@130 {
						reg = <0x130 0x20>;
					};

					user_key2: user-key@150 {
						reg = <0x150 0x20>;
					};

					user_key3: user-key@170 {
						reg = <0x170 0x20>;
					};

					user_key4: user-key@190 {
						reg = <0x190 0x20>;
					};

					user_key5: user-key@1b0 {
						reg = <0x1b0 0x20>;
					};

					user_key6: user-key@1d0 {
						reg = <0x1d0 0x20>;
					};

					user_key7: user-key@1f0 {
						reg = <0x1f0 0x20>;
					};
				};
			};
		};
	};
};

&psv_cortexa72_0 {
	clocks = <&versal_clk ACPU>;
};

&can0 {
	clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_CAN_FD_0>;
};

&can1 {
	clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_CAN_FD_1>;
};

&gem0 {
	clocks = <&versal_clk LPD_LSBUS>,
		 <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>,
		 <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>;
	power-domains = <&versal_firmware PM_DEV_GEM_0>;
};

&gem1 {
	clocks = <&versal_clk LPD_LSBUS>,
		 <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>,
		 <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>;
	power-domains = <&versal_firmware PM_DEV_GEM_1>;
};

&gpio0 {
	clocks = <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_GPIO>;
};

&gpio1 {
	clocks = <&versal_clk PMC_LSBUS_REF>;
	power-domains = <&versal_firmware PM_DEV_GPIO_PMC>;
};

&i2c0 {
	clocks = <&versal_clk I2C0_REF>;
	power-domains = <&versal_firmware PM_DEV_I2C_0>;
};

&i2c1 {
	clocks = <&versal_clk I2C1_REF>;
	power-domains = <&versal_firmware PM_DEV_I2C_1>;
};

&i2c2 {
	clocks = <&versal_clk I2C_REF>;
	power-domains = <&versal_firmware PM_DEV_I2C_PMC>;
};

&lpd_dma_chan0 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_0>;
};

&lpd_dma_chan1 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_1>;
};

&lpd_dma_chan2 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_2>;
};

&lpd_dma_chan3 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_3>;
};

&lpd_dma_chan4 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_4>;
};

&lpd_dma_chan5 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_5>;
};

&lpd_dma_chan6 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_6>;
};

&lpd_dma_chan7 {
	clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_ADMA_7>;
};

&qspi {
	clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_QSPI>;
};

&ospi {
	clocks = <&versal_clk OSPI_REF>;
	power-domains = <&versal_firmware PM_DEV_OSPI>;
	reset-names = "qspi";
	resets = <&versal_reset VERSAL_RST_OSPI>;
};

&rtc {
	clocks = <&rtc_clk>;
	clock-names = "rtc";
	power-domains = <&versal_firmware PM_DEV_RTC>;
};

&serial0 {
	clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_UART_0>;
};

&serial1 {
	clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_UART_1>;
};

&sdhci0 {
	clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>,
		<&versal_clk SD_DLL_REF>;
	power-domains = <&versal_firmware PM_DEV_SDIO_0>;
};

&sdhci1 {
	clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>,
		<&versal_clk SD_DLL_REF>;
	power-domains = <&versal_firmware PM_DEV_SDIO_1>;
};

&spi0 {
	clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_SPI_0>;
};

&spi1 {
	clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_SPI_1>;
};

&ttc0 {
	clocks = <&versal_clk TTC0>;
	power-domains = <&versal_firmware PM_DEV_TTC_0>;
};

&ttc1 {
	clocks = <&versal_clk TTC1>;
	power-domains = <&versal_firmware PM_DEV_TTC_1>;
};

&ttc2 {
	clocks = <&versal_clk TTC2>;
	power-domains = <&versal_firmware PM_DEV_TTC_2>;
};

&ttc3 {
	clocks = <&versal_clk TTC3>;
	power-domains = <&versal_firmware PM_DEV_TTC_3>;
};

&usb0 {
	clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>;
	power-domains = <&versal_firmware PM_DEV_USB_0>;
	resets = <&versal_reset VERSAL_RST_USB_0>;
};

&dwc3_0 {
	clocks = <&versal_clk USB0_BUS_REF>;
};

&watchdog {
	clocks = <&versal_clk FPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_SWDT_FPD>;
};

&watchdog1 {
	clocks = <&versal_clk LPD_LSBUS>;
	power-domains = <&versal_firmware PM_DEV_SWDT_LPD>;
};

&sysmon0 {
	xlnx,nodeid = <PM_REGNODE_SYSMON_ROOT_0>;
};

&sysmon1 {
	xlnx,nodeid = <PM_REGNODE_SYSMON_ROOT_1>;
};

&sysmon2 {
	xlnx,nodeid = <PM_REGNODE_SYSMON_ROOT_2>;
};

&sysmon3 {
	xlnx,nodeid = <PM_REGNODE_SYSMON_ROOT_3>;
};

&fpd_funnel {
	clocks = <&versal_clk LPD_LSBUS>;
};

&fpd_etf {
	clocks = <&versal_clk LPD_LSBUS>;
};

&replicator {
	clocks = <&versal_clk LPD_LSBUS>;
};

&etr {
	clocks = <&versal_clk LPD_LSBUS>;
};

&apu_funnel {
	clocks = <&versal_clk LPD_LSBUS>;
};

&apu_etf {
	clocks = <&versal_clk LPD_LSBUS>;
};

&cpu0_debug {
	clocks = <&versal_clk LPD_LSBUS>;
};

&etm0 {
	clocks = <&versal_clk LPD_LSBUS>;
};

&cpu1_debug {
	clocks = <&versal_clk LPD_LSBUS>;
};

&etm1 {
	clocks = <&versal_clk LPD_LSBUS>;
};
