<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2026.1 (64-bit)                              -->
<!-- SW Build 6504319 on Tue Jun 09 04:59:37 MDT 2026                  -->
<!--                                                                         -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
<!-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.   -->
<!-- Jun  9 2026                                                             -->
<!--                                                                             -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file.                                                      -->

<MemInfo Version="1" Minor="9">
  <MemoryArray InstPath="edf_base_pl_i/axi_bram_ctrl_0_bram/inst/gen_xpm.gen_base.xpm_memory_base_inst" MemoryPrimitive="block" MemoryConfiguration="enabled_configuration">
    <MemoryLayout Name="edf_base_pl_i/axi_bram_ctrl_0_bram/inst/gen_xpm.gen_base.xpm_memory_base_inst" CoreMemory_Width="32" MemoryType="RAM_TDP">
      <BRAM MemType="RAMB36" Placement="X2Y8" Read_Width_A="18" Read_Width_B="18" SLR_INDEX="0">
        <DataWidth_PortA MSB="15" LSB="0"/>
        <AddressRange_PortA Begin="0" End="2047"/>
        <BitLayout_PortA pattern="p0_d8_p0_d8"/>
        <DataWidth_PortB MSB="15" LSB="0"/>
        <AddressRange_PortB Begin="0" End="2047"/>
        <BitLayout_PortB pattern="p0_d8_p0_d8"/>
        <Parity ON="false" NumBits="0"/>
      </BRAM>
      <BRAM MemType="RAMB36" Placement="X1Y8" Read_Width_A="18" Read_Width_B="18" SLR_INDEX="0">
        <DataWidth_PortA MSB="31" LSB="16"/>
        <AddressRange_PortA Begin="0" End="2047"/>
        <BitLayout_PortA pattern="p0_d8_p0_d8"/>
        <DataWidth_PortB MSB="31" LSB="16"/>
        <AddressRange_PortB Begin="0" End="2047"/>
        <BitLayout_PortB pattern="p0_d8_p0_d8"/>
        <Parity ON="false" NumBits="0"/>
      </BRAM>
    </MemoryLayout>
  </MemoryArray>
  <Config>
    <Option Name="Part" Val="xcvr1652-vsva2488-2MP-e-S-es1"/>
  </Config>
  <DRC>
    <Rule Name="RDADDRCHANGE" Val="false"/>
  </DRC>
</MemInfo>
