{
  "spec_file_version": 4,
  "info": {
    "device_name": "ve2302",
    "format": "deep"
  },
  "flags": {},
  "modules": {},
  "design": {
    "name": "ve2302_pcie_xdma_wrapper_1",
    "cells": {
      "blp_cips": {
        "type": "ip",
        "vlnv": "xilinx.com:ip:versal_cips:3.4",
        "cells": {
          "blp_cips_pspmc_0": {
            "type": "ps",
            "vlnv": "xilinx.com:ip:pspmc:1.4",
            "destinations": [
              {"name": "blp_cips_pspmc_0_psv_r5_tcm_ram_0", "addr": "0x0", "size": "256K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_atcm", "addr": "0x0", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_1_atcm", "addr": "0x0", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_btcm", "addr": "0x20000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_1_btcm", "addr": "0x20000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_lpd_afi_mem_0", "addr": "0x80000000", "size": "512M"},
              {"name": "blp_cips_pspmc_0_psv_fpd_afi_mem_0", "addr": "0xa4000000", "size": "192M"},
              {"name": "blp_cips_pspmc_0_psv_fpd_afi_mem_2", "addr": "0xb0000000", "size": "256M"},
              {"name": "blp_cips_pspmc_0_psv_pmc_qspi_ospi_flash_0", "addr": "0xc0000000", "size": "512M"},
              {"name": "blp_cips_pspmc_0_psv_pmc_tmr_inject_0", "addr": "0xf0083000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_ram_instr_cntlr", "addr": "0xf0200000", "size": "256K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_ram_data_cntlr", "addr": "0xf0240000", "size": "128K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_tmr_manager_0", "addr": "0xf0283000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_ppu1_mdm_0", "addr": "0xf0310000", "size": "32K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_0", "addr": "0xf0800000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_pmc_cti", "addr": "0xf08d0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_lpd_atm", "addr": "0xf0980000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_lpd_cti", "addr": "0xf09d0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_r50_cti", "addr": "0xf0a10000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_r51_cti", "addr": "0xf0a50000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_fpd_stm", "addr": "0xf0b70000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_fpd_atm", "addr": "0xf0b80000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_fpd_cti1b", "addr": "0xf0bb0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_fpd_cti1c", "addr": "0xf0bc0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_fpd_cti1d", "addr": "0xf0bd0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_apu_fun", "addr": "0xf0c20000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_apu_etf", "addr": "0xf0c30000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_apu_ela", "addr": "0xf0c60000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_apu_cti", "addr": "0xf0ca0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a720_dbg", "addr": "0xf0d00000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a720_cti", "addr": "0xf0d10000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a720_pmu", "addr": "0xf0d20000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a720_etm", "addr": "0xf0d30000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a721_dbg", "addr": "0xf0d40000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a721_cti", "addr": "0xf0d50000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a721_pmu", "addr": "0xf0d60000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_a721_etm", "addr": "0xf0d70000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_rom", "addr": "0xf0f00000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_fun", "addr": "0xf0f20000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_ela2a", "addr": "0xf0f40000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_ela2b", "addr": "0xf0f50000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_ela2c", "addr": "0xf0f60000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_ela2d", "addr": "0xf0f70000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_atm", "addr": "0xf0f80000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_cti2a", "addr": "0xf0fa0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_coresight_cpm_cti2d", "addr": "0xf0fd0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_i2c_0", "addr": "0xf1000000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_ospi_0", "addr": "0xf1010000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_gpio_0", "addr": "0xf1020000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_iou_slcr_0", "addr": "0xf1060000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_global_0", "addr": "0xf1110000", "size": "320K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_analog_0", "addr": "0xf1160000", "size": "192K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_tap", "addr": "0xf11a0000", "size": "128K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_dma_0", "addr": "0xf11c0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_dma_1", "addr": "0xf11d0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_aes", "addr": "0xf11e0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_bbram_ctrl", "addr": "0xf11f0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_rsa", "addr": "0xf1200000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_sha", "addr": "0xf1210000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_slave_boot", "addr": "0xf1220000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_trng", "addr": "0xf1230000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_efuse_ctrl", "addr": "0xf1240000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_efuse_cache", "addr": "0xf1250000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_crp_0", "addr": "0xf1260000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_sysmon_0", "addr": "0xf1270000", "size": "192K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_rtc_0", "addr": "0xf12a0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfu_apb_0", "addr": "0xf12b0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_0", "addr": "0xf12d0000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_1", "addr": "0xf12d2000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_2", "addr": "0xf12d4000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_3", "addr": "0xf12d6000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_4", "addr": "0xf12d8000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_5", "addr": "0xf12da000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_6", "addr": "0xf12dc000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_7", "addr": "0xf12de000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_8", "addr": "0xf12e0000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_9", "addr": "0xf12e2000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_10", "addr": "0xf12e4000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_11", "addr": "0xf12e6000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_12", "addr": "0xf12e8000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_13", "addr": "0xf12ea000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_14", "addr": "0xf12ec000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_cfi_cframe_bcast", "addr": "0xf12ee000", "size": "4K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_xmpu_0", "addr": "0xf12f0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_xppu_npi_0", "addr": "0xf1300000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_xppu_0", "addr": "0xf1310000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_slave_boot_stream", "addr": "0xf2100000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_pmc_ram_npi", "addr": "0xf6000000", "size": "32M"},
              {"name": "blp_cips_pspmc_0_psv_cpm", "addr": "0xfc000000", "size": "16M"},
              {"name": "blp_cips_pspmc_0_psv_fpd_maincci_0", "addr": "0xfd000000", "size": "1M"},
              {"name": "blp_cips_pspmc_0_psv_crf_0", "addr": "0xfd1a0000", "size": "1280K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_afi_0", "addr": "0xfd360000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_afi_2", "addr": "0xfd380000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_slave_xmpu_0", "addr": "0xfd390000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_apu_0", "addr": "0xfd5c0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_cci_0", "addr": "0xfd5e0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_smmu_0", "addr": "0xfd5f0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_slcr_0", "addr": "0xfd610000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_slcr_secure_0", "addr": "0xfd690000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_fpd_gpv_0", "addr": "0xfd700000", "size": "1M"},
              {"name": "blp_cips_pspmc_0_psv_fpd_smmutcu_0", "addr": "0xfd800000", "size": "8M"},
              {"name": "blp_cips_pspmc_0_psv_sbsauart_0", "addr": "0xff000000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_sbsauart_1", "addr": "0xff010000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_spi_0", "addr": "0xff040000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_lpd_iou_slcr_0", "addr": "0xff080000", "size": "128K"},
              {"name": "blp_cips_pspmc_0_psv_lpd_iou_secure_slcr_0", "addr": "0xff0a0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_gpio_2", "addr": "0xff0b0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ttc_0", "addr": "0xff0e0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ttc_1", "addr": "0xff0f0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ttc_2", "addr": "0xff100000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ttc_3", "addr": "0xff110000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_scntr_0", "addr": "0xff130000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_scntrs_0", "addr": "0xff140000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_psm", "addr": "0xff310000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_pmc", "addr": "0xff320000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_0", "addr": "0xff330000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_1", "addr": "0xff340000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_2", "addr": "0xff350000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_3", "addr": "0xff360000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_4", "addr": "0xff370000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_5", "addr": "0xff380000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_pmc_nobuf", "addr": "0xff390000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ipi_6", "addr": "0xff3a0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_lpd_slcr_0", "addr": "0xff410000", "size": "1M"},
              {"name": "blp_cips_pspmc_0_psv_lpd_slcr_secure_0", "addr": "0xff510000", "size": "256K"},
              {"name": "blp_cips_pspmc_0_psv_crl_0", "addr": "0xff5e0000", "size": "3M"},
              {"name": "blp_cips_pspmc_0_psv_xram_ctrl_1", "addr": "0xff8e0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_xram_ctrl_2", "addr": "0xff8f0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_xram_ctrl_3", "addr": "0xff900000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_xram_ctrl_4", "addr": "0xff910000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_xram_xmpu_bank_1", "addr": "0xff930000", "size": "16K"},
              {"name": "blp_cips_pspmc_0_psv_xram_xmpu_bank_2", "addr": "0xff934000", "size": "16K"},
              {"name": "blp_cips_pspmc_0_psv_xram_xmpu_bank_3", "addr": "0xff938000", "size": "16K"},
              {"name": "blp_cips_pspmc_0_psv_xram_xmpu_bank_4", "addr": "0xff93c000", "size": "16K"},
              {"name": "blp_cips_pspmc_0_psv_xram_gpv", "addr": "0xff940000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_xram_global_ctrl", "addr": "0xff950000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ocm_ctrl", "addr": "0xff960000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_xram_atm", "addr": "0xff970000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_ocm_xmpu_0", "addr": "0xff980000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_lpd_xppu_0", "addr": "0xff990000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_rpu_0", "addr": "0xff9a0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_lpd_afi_0", "addr": "0xff9b0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_0", "addr": "0xffa80000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_1", "addr": "0xffa90000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_2", "addr": "0xffaa0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_3", "addr": "0xffab0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_4", "addr": "0xffac0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_5", "addr": "0xffad0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_6", "addr": "0xffae0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_adma_7", "addr": "0xffaf0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_psm_ram_instr_cntlr", "addr": "0xffc00000", "size": "128K"},
              {"name": "blp_cips_pspmc_0_psv_psm_ram_data_cntlr", "addr": "0xffc20000", "size": "128K"},
              {"name": "blp_cips_pspmc_0_psv_psm_global_reg", "addr": "0xffc90000", "size": "60K"},
              {"name": "blp_cips_pspmc_0_psv_psm_tmr_manager_0", "addr": "0xffcc0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_psm_tmr_inject_0", "addr": "0xffcd0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_tcm_ram_global", "addr": "0xffe00000", "size": "256K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_atcm_global", "addr": "0xffe00000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_atcm_lockstep", "addr": "0xffe10000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_btcm_global", "addr": "0xffe20000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_btcm_lockstep", "addr": "0xffe30000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_instruction_cache", "addr": "0xffe40000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_0_data_cache", "addr": "0xffe50000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_1_atcm_global", "addr": "0xffe90000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_1_btcm_global", "addr": "0xffeb0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_1_instruction_cache", "addr": "0xffec0000", "size": "64K"},
              {"name": "blp_cips_pspmc_0_psv_r5_1_data_cache", "addr": "0xffed0000", "size": "64K"}
            ],
            "flags": {"BOOT_SECONDARY_PCIE_ENABLE": false, "C_GEM_TSU_ENABLE": true, "C_LPD_GPIO_EMIO_ENABLE": false, "C_PL_SEM_GPO_ENABLE": false, "C_PMC_GPIO_EMIO_ENABLE": false, "C_PMC_I2CPMC_PERIPHERAL": "0", "C_PS_I2C0_PERIPHERAL_ENABLE": false, "C_PS_I2C1_PERIPHERAL_ENABLE": false, "C_PS_PMU_PERIPHERAL_ENABLE": false, "C_PS_TRACE_PERIPHERAL": "0", "PCIE_APERTURES_DUAL_ENABLE": false, "PCIE_APERTURES_SINGLE_ENABLE": false, "PL_SEM_GPIO_ENABLE": false, "PMC_GPIO0_MIO_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 0 .. 25}}}", "PMC_GPIO0_MIO_PERIPHERAL_ENABLE": false, "PMC_GPIO1_MIO_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 26 .. 51}}}", "PMC_GPIO1_MIO_PERIPHERAL_ENABLE": false, "PMC_GPIO_EMIO_PERIPHERAL_ENABLE": false, "PMC_GPI_ENABLE": false, "PMC_GPO_ENABLE": false, "PMC_HSM0_CLK_ENABLE": true, "PMC_HSM0_CLK_OUT_ENABLE": false, "PMC_HSM1_CLK_ENABLE": true, "PMC_HSM1_CLK_OUT_ENABLE": false, "PMC_I2CPMC_PERIPHERAL": "{{ENABLE 1} {IO {PMC_MIO 18 .. 19}}}", "PMC_I2CPMC_PERIPHERAL_ENABLE": true, "PMC_OSPI_PERIPHERAL": "{{ENABLE 1} {IO {PMC_MIO 0 .. 11}} {MODE Single}}", "PMC_OSPI_PERIPHERAL_ENABLE": true, "PMC_QSPI_PERIPHERAL_ENABLE": false, "PMC_SD0_PERIPHERAL": "{{CLK_100_SDR_OTAP_DLY 0x00} {CLK_200_SDR_OTAP_DLY 0x00} {CLK_50_DDR_ITAP_DLY 0x00} {CLK_50_DDR_OTAP_DLY 0x00} {CLK_50_SDR_ITAP_DLY 0x00} {CLK_50_SDR_OTAP_DLY 0x00} {ENABLE 0} {IO {PMC_MIO 13 .. 25}}}", "PMC_SD0_PERIPHERAL_ENABLE": false, "PMC_SD1_PERIPHERAL": "{{CLK_100_SDR_OTAP_DLY 0x00} {CLK_200_SDR_OTAP_DLY 0x00} {CLK_50_DDR_ITAP_DLY 0x00} {CLK_50_DDR_OTAP_DLY 0x00} {CLK_50_SDR_ITAP_DLY 0x00} {CLK_50_SDR_OTAP_DLY 0x00} {ENABLE 0} {IO {PMC_MIO 0 .. 11}}}", "PMC_SD1_PERIPHERAL_ENABLE": false, "PMC_SMAP_PERIPHERAL": "{{ENABLE 0} {IO {32 Bit}}}", "PMC_SMAP_PERIPHERAL_ENABLE": false, "PMC_TAMPER_EXTMIO_ENABLE": false, "PMC_TAMPER_GLITCHDETECT_ENABLE": false, "PMC_TAMPER_JTAGDETECT_ENABLE": false, "PMC_TAMPER_SUP_0_31_ENABLE": false, "PMC_TAMPER_TEMPERATURE_ENABLE": false, "PMC_WDT_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 0}}}", "PMC_WDT_PERIPHERAL_ENABLE": false, "PSPMC_MANUAL_CLK_ENABLE": false, "PS_CAN0_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 8 .. 9}}}", "PS_CAN0_PERIPHERAL_ENABLE": false, "PS_CAN1_PERIPHERAL": "{{ENABLE 0} {IO {PS_MIO 16 .. 17}}}", "PS_CAN1_PERIPHERAL_ENABLE": false, "PS_DDRC_ENABLE": true, "PS_ENET0_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 26 .. 37}}}", "PS_ENET0_PERIPHERAL_ENABLE": false, "PS_ENET1_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 38 .. 49}}}", "PS_ENET1_PERIPHERAL_ENABLE": false, "PS_GEM_TSU": "{{ENABLE 0} {IO {PS_MIO 24}}}", "PS_GEM_TSU_ENABLE": false, "PS_GEN_IPI0_ENABLE": true, "PS_GEN_IPI0_MASTER": "A72", "PS_GEN_IPI1_ENABLE": true, "PS_GEN_IPI1_MASTER": "A72", "PS_GEN_IPI2_ENABLE": true, "PS_GEN_IPI2_MASTER": "A72", "PS_GEN_IPI3_ENABLE": true, "PS_GEN_IPI3_MASTER": "R5_0", "PS_GEN_IPI4_ENABLE": true, "PS_GEN_IPI4_MASTER": "R5_0", "PS_GEN_IPI5_ENABLE": true, "PS_GEN_IPI5_MASTER": "R5_1", "PS_GEN_IPI6_ENABLE": true, "PS_GEN_IPI6_MASTER": "R5_1", "PS_GEN_IPI_PMCNOBUF_ENABLE": true, "PS_GEN_IPI_PMCNOBUF_MASTER": "PMC", "PS_GEN_IPI_PMC_ENABLE": true, "PS_GEN_IPI_PMC_MASTER": "PMC", "PS_GEN_IPI_PSM_ENABLE": true, "PS_GEN_IPI_PSM_MASTER": "PSM", "PS_GPIO2_MIO_PERIPHERAL": "{{ENABLE 0} {IO {PS_MIO 0 .. 25}}}", "PS_GPIO2_MIO_PERIPHERAL_ENABLE": false, "PS_GPIO_EMIO_PERIPHERAL_ENABLE": false, "PS_I2C0_PERIPHERAL": "{{ENABLE 0} {IO {PS_MIO 2 .. 3}}}", "PS_I2C0_PERIPHERAL_ENABLE": false, "PS_I2C1_PERIPHERAL": "{{ENABLE 0} {IO {PS_MIO 0 .. 1}}}", "PS_I2C1_PERIPHERAL_ENABLE": false, "PS_I2CSYSMON_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 35 .. 36}}}", "PS_I2CSYSMON_PERIPHERAL_ENABLE": false, "PS_KAT_ENABLE": true, "PS_LPD_DMA_CHANNEL_ENABLE": false, "PS_LPD_DMA_ENABLE": false, "PS_PCIE1_PERIPHERAL_ENABLE": false, "PS_PCIE2_PERIPHERAL_ENABLE": false, "PS_PCIE_PERIPHERAL_ENABLE": false, "PS_PMU_PERIPHERAL_ENABLE": false, "PS_PS_ENABLE": false, "PS_RED_KEY_CLEAR_ENABLE": false, "PS_SMON_PL_PORTS_ENABLE": false, "PS_SPI0": "{{GRP_SS0_ENABLE 1} {GRP_SS0_IO {PMC_MIO 41}} {GRP_SS1_ENABLE 0} {GRP_SS1_IO {PMC_MIO 14}} {GRP_SS2_ENABLE 0} {GRP_SS2_IO {PMC_MIO 13}} {PERIPHERAL_ENABLE 1} {PERIPHERAL_IO {PMC_MIO 38 .. 43}}}", "PS_SPI0_GRP_SS0_ENABLE": true, "PS_SPI0_GRP_SS1_ENABLE": false, "PS_SPI0_GRP_SS2_ENABLE": false, "PS_SPI0_PERIPHERAL_ENABLE": true, "PS_SPI1": "{{GRP_SS0_ENABLE 0} {GRP_SS0_IO {PS_MIO 9}} {GRP_SS1_ENABLE 0} {GRP_SS1_IO {PS_MIO 8}} {GRP_SS2_ENABLE 0} {GRP_SS2_IO {PS_MIO 7}} {PERIPHERAL_ENABLE 0} {PERIPHERAL_IO {PS_MIO 6 .. 11}}}", "PS_SPI1_GRP_SS0_ENABLE": false, "PS_SPI1_GRP_SS1_ENABLE": false, "PS_SPI1_GRP_SS2_ENABLE": false, "PS_SPI1_PERIPHERAL_ENABLE": false, "PS_TRACE_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 30 .. 47}}}", "PS_TRACE_PERIPHERAL_ENABLE": false, "PS_TTC0_PERIPHERAL_ENABLE": true, "PS_TTC1_PERIPHERAL_ENABLE": true, "PS_TTC2_PERIPHERAL_ENABLE": true, "PS_TTC3_PERIPHERAL_ENABLE": true, "PS_UART0_PERIPHERAL": "{{ENABLE 1} {IO {PMC_MIO 16 .. 17}}}", "PS_UART0_PERIPHERAL_ENABLE": true, "PS_UART1_PERIPHERAL": "{{ENABLE 1} {IO {PMC_MIO 20 .. 21}}}", "PS_UART1_PERIPHERAL_ENABLE": true, "PS_USB3_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 13 .. 25}}}", "PS_USB3_PERIPHERAL_ENABLE": false, "PS_WWDT0_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 0 .. 5}}}", "PS_WWDT0_PERIPHERAL_ENABLE": false, "PS_WWDT1_PERIPHERAL": "{{ENABLE 0} {IO {PMC_MIO 6 .. 11}}}", "PS_WWDT1_PERIPHERAL_ENABLE": false, "SLR1_PMC_HSM0_CLK_ENABLE": true, "SLR1_PMC_HSM0_CLK_OUT_ENABLE": false, "SLR1_PMC_HSM1_CLK_ENABLE": true, "SLR1_PMC_HSM1_CLK_OUT_ENABLE": false, "SLR2_PMC_HSM0_CLK_ENABLE": true, "SLR2_PMC_HSM0_CLK_OUT_ENABLE": false, "SLR2_PMC_HSM1_CLK_ENABLE": true, "SLR2_PMC_HSM1_CLK_OUT_ENABLE": false, "SLR3_PMC_HSM0_CLK_ENABLE": true, "SLR3_PMC_HSM0_CLK_OUT_ENABLE": false, "SLR3_PMC_HSM1_CLK_ENABLE": true, "SLR3_PMC_HSM1_CLK_OUT_ENABLE": false, "SMON_INT_MEASUREMENT_ALARM_ENABLE": false, "SMON_INT_MEASUREMENT_AVG_ENABLE": false, "SMON_INT_MEASUREMENT_ENABLE": false, "SMON_MUX_ADDR_ENABLE": false}
          }
        }
      }
    },
    "base_protection": {}
  }
}