#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_XCANFD_NUM_INSTANCES 2

/* Definitions for peripheral CAN0 */
#define XPAR_CAN0_COMPATIBLE "xlnx,canfd-2.0"
#define XPAR_CAN0_BASEADDR 0xf1980000
#define XPAR_CAN0_HIGHADDR 0xf1985fff
#define XPAR_CAN0_RX_MODE 0x0
#define XPAR_CAN0_NUM_OF_RX_MB_BUF 0x30
#define XPAR_CAN0_NUM_OF_TX_BUF 0x20
#define XPAR_CAN0_INTERRUPTS 0x401b
#define XPAR_CAN0_CAN_CLK_FREQ_HZ 0x98961be

/* Canonical definitions for peripheral CAN0 */
#define XPAR_XCANFD_0_BASEADDR 0xf1980000
#define XPAR_XCANFD_0_HIGHADDR 0xf1985fff
#define XPAR_XCANFD_0_COMPATIBLE "xlnx,canfd-2.0"
#define XPAR_XCANFD_0_CAN_CLK_FREQ_HZ 0x98961be
#define XPAR_XCANFD_0_INTERRUPTS 0x401b
#define XPAR_XCANFD_0_NUM_OF_RX_MB_BUF 0x30
#define XPAR_XCANFD_0_NUM_OF_TX_BUF 0x20
#define XPAR_XCANFD_0_RX_MODE 0x0

/* Definitions for peripheral CAN1 */
#define XPAR_CAN1_COMPATIBLE "xlnx,canfd-2.0"
#define XPAR_CAN1_BASEADDR 0xf1990000
#define XPAR_CAN1_HIGHADDR 0xf1995fff
#define XPAR_CAN1_RX_MODE 0x0
#define XPAR_CAN1_NUM_OF_RX_MB_BUF 0x30
#define XPAR_CAN1_NUM_OF_TX_BUF 0x20
#define XPAR_CAN1_INTERRUPTS 0x401c
#define XPAR_CAN1_CAN_CLK_FREQ_HZ 0x98961be

/* Canonical definitions for peripheral CAN1 */
#define XPAR_XCANFD_1_BASEADDR 0xf1990000
#define XPAR_XCANFD_1_HIGHADDR 0xf1995fff
#define XPAR_XCANFD_1_COMPATIBLE "xlnx,canfd-2.0"
#define XPAR_XCANFD_1_CAN_CLK_FREQ_HZ 0x98961be
#define XPAR_XCANFD_1_INTERRUPTS 0x401c
#define XPAR_XCANFD_1_NUM_OF_RX_MB_BUF 0x30
#define XPAR_XCANFD_1_NUM_OF_TX_BUF 0x20
#define XPAR_XCANFD_1_RX_MODE 0x0

#define XPAR_XCFRAME_NUM_INSTANCES 1

/* Definitions for peripheral PMC_CFI_CFRAME_0 */
#define XPAR_PMC_CFI_CFRAME_0_COMPATIBLE "xlnx,psx-pmc-cfi-cframe-11.0"
#define XPAR_PMC_CFI_CFRAME_0_BASEADDR 0xf12d0000
#define XPAR_PMC_CFI_CFRAME_0_HIGHADDR 0xf12d0fff

/* Canonical definitions for peripheral PMC_CFI_CFRAME_0 */
#define XPAR_XCFRAME_0_BASEADDR 0xf12d0000
#define XPAR_XCFRAME_0_HIGHADDR 0xf12d0fff
#define XPAR_XCFRAME_0_COMPATIBLE "xlnx,psx-pmc-cfi-cframe-11.0"

#define XPAR_XCFUPMC_NUM_INSTANCES 1

/* Definitions for peripheral PMC_CFU_APB_0 */
#define XPAR_PMC_CFU_APB_0_COMPATIBLE "xlnx,psx-pmc-cfu-apb-11.0"
#define XPAR_PMC_CFU_APB_0_BASEADDR 0xf12b0000
#define XPAR_PMC_CFU_APB_0_HIGHADDR 0xf12bffff

/* Canonical definitions for peripheral PMC_CFU_APB_0 */
#define XPAR_XCFUPMC_0_BASEADDR 0xf12b0000
#define XPAR_XCFUPMC_0_HIGHADDR 0xf12bffff
#define XPAR_XCFUPMC_0_COMPATIBLE "xlnx,psx-pmc-cfu-apb-11.0"

#define XPAR_XCSUDMA_NUM_INSTANCES 2

/* Definitions for peripheral DMA0 */
#define XPAR_DMA0_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_DMA0_BASEADDR 0xf11c0000
#define XPAR_DMA0_HIGHADDR 0xf11cffff
#define XPAR_DMA0_DMA_TYPE 0x1
#define XPAR_DMA0_INTERRUPTS 0x40be

/* Canonical definitions for peripheral DMA0 */
#define XPAR_XCSUDMA_0_BASEADDR 0xf11c0000
#define XPAR_XCSUDMA_0_HIGHADDR 0xf11cffff
#define XPAR_XCSUDMA_0_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_XCSUDMA_0_DMA_TYPE 0x1
#define XPAR_XCSUDMA_0_INTERRUPTS 0x40be

/* Definitions for peripheral DMA1 */
#define XPAR_DMA1_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_DMA1_BASEADDR 0xf11d0000
#define XPAR_DMA1_HIGHADDR 0xf11dffff
#define XPAR_DMA1_DMA_TYPE 0x2
#define XPAR_DMA1_INTERRUPTS 0x40bf

/* Canonical definitions for peripheral DMA1 */
#define XPAR_XCSUDMA_1_BASEADDR 0xf11d0000
#define XPAR_XCSUDMA_1_HIGHADDR 0xf11dffff
#define XPAR_XCSUDMA_1_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_XCSUDMA_1_DMA_TYPE 0x2
#define XPAR_XCSUDMA_1_INTERRUPTS 0x40bf

#define XPAR_XEMACPS_NUM_INSTANCES 1

/* Definitions for peripheral GEM0 */
#define XPAR_GEM0_COMPATIBLE "xlnx,versal-gem"
#define XPAR_GEM0_BASEADDR 0xf19e0000
#define XPAR_GEM0_HIGHADDR 0xf19e0fff
#define XPAR_GEM0_INTERRUPTS 0x4027
#define XPAR_GEM0_INTERRUPTS_1 0x4027
#define XPAR_GEM0_CLOCKS 0x31
#define XPAR_GEM0_PHY_MODE "rgmii-id"
#define XPAR_GEM0_PHY_HANDLE 0x1

/* Canonical definitions for peripheral GEM0 */
#define XPAR_XEMACPS_0_BASEADDR 0xf19e0000
#define XPAR_XEMACPS_0_HIGHADDR 0xf19e0fff
#define XPAR_XEMACPS_0_COMPATIBLE "xlnx,versal-gem"
#define XPAR_XEMACPS_0_CLOCKS 0x31
#define XPAR_XEMACPS_0_INTERRUPTS 0x4027
#define XPAR_XEMACPS_0_PHY_MODE "rgmii-id"
#define XPAR_XEMACPS_0_PHY_HANDLE 0x1

#define XPAR_XGPIOPS_NUM_INSTANCES 1

/* Definitions for peripheral GPIO1 */
#define XPAR_GPIO1_COMPATIBLE "xlnx,pmc-gpio-1.0"
#define XPAR_GPIO1_BASEADDR 0xf1020000
#define XPAR_GPIO1_HIGHADDR 0xf1020fff
#define XPAR_GPIO1_INTERRUPTS 0x40b4

/* Canonical definitions for peripheral GPIO1 */
#define XPAR_XGPIOPS_0_BASEADDR 0xf1020000
#define XPAR_XGPIOPS_0_HIGHADDR 0xf1020fff
#define XPAR_XGPIOPS_0_COMPATIBLE "xlnx,pmc-gpio-1.0"
#define XPAR_XGPIOPS_0_INTERRUPTS 0x40b4

#define XPAR_XI3CPSX_NUM_INSTANCES 3

/* Definitions for peripheral I3C0 */
#define XPAR_I3C0_COMPATIBLE "snps,dw-i3c-master-1.00a"
#define XPAR_I3C0_BASEADDR 0xf1948000
#define XPAR_I3C0_HIGHADDR 0xf1948fff
#define XPAR_I3C0_INTERRUPTS 0x4015
#define XPAR_I3C0_I3C_CLK_FREQ_HZ 0x98961be
#define XPAR_I3C0_DEVICE_COUNT 0x0

/* Canonical definitions for peripheral I3C0 */
#define XPAR_XI3CPSX_0_BASEADDR 0xf1948000
#define XPAR_XI3CPSX_0_HIGHADDR 0xf1948fff
#define XPAR_XI3CPSX_0_COMPATIBLE "snps,dw-i3c-master-1.00a"
#define XPAR_XI3CPSX_0_DEVICE_COUNT 0x0
#define XPAR_XI3CPSX_0_INTERRUPTS 0x4015
#define XPAR_XI3CPSX_0_I3C_CLK_FREQ_HZ 0x98961be

/* Definitions for peripheral I3C1 */
#define XPAR_I3C1_COMPATIBLE "snps,dw-i3c-master-1.00a"
#define XPAR_I3C1_BASEADDR 0xf1958000
#define XPAR_I3C1_HIGHADDR 0xf1958fff
#define XPAR_I3C1_INTERRUPTS 0x4016
#define XPAR_I3C1_I3C_CLK_FREQ_HZ 0x98961be
#define XPAR_I3C1_DEVICE_COUNT 0x0

/* Canonical definitions for peripheral I3C1 */
#define XPAR_XI3CPSX_1_BASEADDR 0xf1958000
#define XPAR_XI3CPSX_1_HIGHADDR 0xf1958fff
#define XPAR_XI3CPSX_1_COMPATIBLE "snps,dw-i3c-master-1.00a"
#define XPAR_XI3CPSX_1_DEVICE_COUNT 0x0
#define XPAR_XI3CPSX_1_INTERRUPTS 0x4016
#define XPAR_XI3CPSX_1_I3C_CLK_FREQ_HZ 0x98961be

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0_COMPATIBLE "xlnx,psx-i3c-11.0"
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0_BASEADDR 0xf1000000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0_HIGHADDR 0xf100ffff
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0_I3C_CLK_FREQ_HZ 0x2faf080
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0_DEVICE_COUNT 0x0

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_I3C_0 */
#define XPAR_XI3CPSX_2_BASEADDR 0xf1000000
#define XPAR_XI3CPSX_2_HIGHADDR 0xf100ffff
#define XPAR_XI3CPSX_2_COMPATIBLE "xlnx,psx-i3c-11.0"
#define XPAR_XI3CPSX_2_DEVICE_COUNT 0x0
#define XPAR_XI3CPSX_2_I3C_CLK_FREQ_HZ 0x2faf080

#define XPAR_XIOMODULE_NUM_INSTANCES 1

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_COMPATIBLE "xlnx,psx-iomodule-11.0"
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_BASEADDR 0xebc80000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_HIGHADDR 0xebc87fff
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_HAS_FAST 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_BASE_VECTORS 0xebc00000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_ADDR_WIDTH 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_OPTIONS 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_CLOCK_FREQ 0x5f5e100
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_BAUDRATE 0x1c200
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_USED_0 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_USED_1 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_USED_2 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_USED_3 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_SIZE_0 32
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_SIZE_1 32
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_SIZE_2 32
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_SIZE_3 32
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_MASK_0 4294967295
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_MASK_1 4294967295
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_MASK_2 4294967295
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_MASK_3 4294967295
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_PRESCALER_0 9
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_PRESCALER_1 0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_PRESCALER_2 9
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_PRESCALER_3 0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_READABLE_0 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_READABLE_1 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_READABLE_2 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT_READABLE_3 1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO_INIT_0 0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO_INIT_1 0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO_INIT_2 0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO_INIT_3 0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_MAX_INTR_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_INTR_SIZE 0x10
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_USE_EXT_INTR 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_INTC_POSITIVE 0xffff
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_PROG_BAUDRATE 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_DATA_BITS 0x8
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_USE_PARITY 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_ODD_PARITY 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_RX_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_TX_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_UART_RX 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_UART_TX 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_UART_ERROR_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_FIT1 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT1_NO_CLOCKS 0x1848
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT1_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_FIT2 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT2_NO_CLOCKS 0x1848
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT2_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_FIT3 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT3_NO_CLOCKS 0x1848
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT3_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_FIT4 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT4_NO_CLOCKS 0x1848
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FIT4_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_PIT1 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT1_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT1_READABLE 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT1_PRESCALER 0x9
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT1_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_PIT2 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT2_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT2_READABLE 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT2_PRESCALER 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT2_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_PIT3 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT3_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT3_READABLE 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT3_PRESCALER 0x9
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT3_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_PIT4 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT4_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT4_READABLE 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT4_PRESCALER 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_PIT4_INTERRUPT 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPO1 0x1
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO1_SIZE 0x3
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO1_INIT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPO2 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO2_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO2_INIT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPO3 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO3_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO3_INIT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPO4 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO4_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPO4_INIT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPI1 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI1_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI1_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPI2 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI2_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI2_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPI3 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI3_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI3_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_GPI4 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI4_SIZE 0x20
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_GPI4_INTERRUPT 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_USE_IO_BUS 0x0
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_IO_MASK 0xfffe0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_FREQ 0x5f5e100
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_IO_BASEADDR_0 4294967295
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0_IO_BASEADDR_1 4294967295

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_IOMODULE_0 */
#define XPAR_XIOMODULE_0_BASEADDR 0xebc80000
#define XPAR_XIOMODULE_0_HIGHADDR 0xebc87fff
#define XPAR_XIOMODULE_0_COMPATIBLE "xlnx,psx-iomodule-11.0"
#define XPAR_XIOMODULE_0_CLOCK_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_FIT1_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT1_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT2_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT2_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT3_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT3_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT4_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT4_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_GPO_INIT_0 0
#define XPAR_XIOMODULE_0_GPO_INIT_1 0
#define XPAR_XIOMODULE_0_GPO_INIT_2 0
#define XPAR_XIOMODULE_0_GPO_INIT_3 0
#define XPAR_XIOMODULE_0_GPO1_SIZE 0x3
#define XPAR_XIOMODULE_0_GPO1_INIT 0x0
#define XPAR_XIOMODULE_0_GPO2_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO2_INIT 0x0
#define XPAR_XIOMODULE_0_GPO3_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO3_INIT 0x0
#define XPAR_XIOMODULE_0_GPO4_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO4_INIT 0x0
#define XPAR_XIOMODULE_0_GPI1_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI1_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI2_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI2_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI3_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI3_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI4_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI4_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_INTC_HAS_FAST 0x0
#define XPAR_XIOMODULE_0_INTC_BASE_VECTORS 0xebc00000
#define XPAR_XIOMODULE_0_INTC_ADDR_WIDTH 0x20
#define XPAR_XIOMODULE_0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_XIOMODULE_0_INTC_INTR_SIZE 0x10
#define XPAR_XIOMODULE_0_INTC_USE_EXT_INTR 0x1
#define XPAR_XIOMODULE_0_INTC_POSITIVE 0xffff
#define XPAR_XIOMODULE_0_IO_MASK 0xfffe0000
#define XPAR_XIOMODULE_0_IO_BASEADDR_0 4294967295
#define XPAR_XIOMODULE_0_IO_BASEADDR_1 4294967295
#define XPAR_XIOMODULE_0_MAX_INTR_SIZE 0x20
#define XPAR_XIOMODULE_0_OPTIONS 0x1
#define XPAR_XIOMODULE_0_PIT_USED_0 1
#define XPAR_XIOMODULE_0_PIT_USED_1 1
#define XPAR_XIOMODULE_0_PIT_USED_2 1
#define XPAR_XIOMODULE_0_PIT_USED_3 1
#define XPAR_XIOMODULE_0_PIT_SIZE_0 32
#define XPAR_XIOMODULE_0_PIT_SIZE_1 32
#define XPAR_XIOMODULE_0_PIT_SIZE_2 32
#define XPAR_XIOMODULE_0_PIT_SIZE_3 32
#define XPAR_XIOMODULE_0_PIT_MASK_0 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_1 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_2 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_3 4294967295
#define XPAR_XIOMODULE_0_PIT_PRESCALER_0 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_1 0
#define XPAR_XIOMODULE_0_PIT_PRESCALER_2 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_3 0
#define XPAR_XIOMODULE_0_PIT_READABLE_0 1
#define XPAR_XIOMODULE_0_PIT_READABLE_1 1
#define XPAR_XIOMODULE_0_PIT_READABLE_2 1
#define XPAR_XIOMODULE_0_PIT_READABLE_3 1
#define XPAR_XIOMODULE_0_PIT1_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT1_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT1_PRESCALER 0x9
#define XPAR_XIOMODULE_0_PIT1_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT2_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT2_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT2_PRESCALER 0x0
#define XPAR_XIOMODULE_0_PIT2_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT3_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT3_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT3_PRESCALER 0x9
#define XPAR_XIOMODULE_0_PIT3_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT4_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT4_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT4_PRESCALER 0x0
#define XPAR_XIOMODULE_0_PIT4_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_UART_BAUDRATE 0x1c200
#define XPAR_XIOMODULE_0_UART_PROG_BAUDRATE 0x1
#define XPAR_XIOMODULE_0_UART_DATA_BITS 0x8
#define XPAR_XIOMODULE_0_UART_USE_PARITY 0x0
#define XPAR_XIOMODULE_0_UART_ODD_PARITY 0x0
#define XPAR_XIOMODULE_0_UART_RX_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_UART_TX_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_USE_UART_RX 0x1
#define XPAR_XIOMODULE_0_USE_UART_TX 0x1
#define XPAR_XIOMODULE_0_UART_ERROR_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_USE_FIT1 0x0
#define XPAR_XIOMODULE_0_USE_FIT2 0x0
#define XPAR_XIOMODULE_0_USE_FIT3 0x0
#define XPAR_XIOMODULE_0_USE_FIT4 0x0
#define XPAR_XIOMODULE_0_USE_PIT1 0x1
#define XPAR_XIOMODULE_0_USE_PIT2 0x1
#define XPAR_XIOMODULE_0_USE_PIT3 0x1
#define XPAR_XIOMODULE_0_USE_PIT4 0x1
#define XPAR_XIOMODULE_0_USE_GPO1 0x1
#define XPAR_XIOMODULE_0_USE_GPO2 0x0
#define XPAR_XIOMODULE_0_USE_GPO3 0x0
#define XPAR_XIOMODULE_0_USE_GPO4 0x0
#define XPAR_XIOMODULE_0_USE_GPI1 0x0
#define XPAR_XIOMODULE_0_USE_GPI2 0x0
#define XPAR_XIOMODULE_0_USE_GPI3 0x0
#define XPAR_XIOMODULE_0_USE_GPI4 0x0
#define XPAR_XIOMODULE_0_USE_IO_BUS 0x0

#define XPAR_XIPIPSU_NUM_INSTANCES 1

/* Definitions for peripheral IPI_PSM */
#define XPAR_IPI_PSM_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_IPI_PSM_BASEADDR 0xeb310000
#define XPAR_IPI_PSM_HIGHADDR 0xeb31ffff
#define XPAR_IPI_PSM_BASEADDR_1 0xeb3f0000
#define XPAR_IPI_PSM_IPI_BITMASK 0x1
#define XPAR_IPI_PSM_IPI_BUF_INDEX 0x0
#define XPAR_IPI_PSM_INTERRUPTS 0x403d
#define XPAR_IPI_PSM_INTR 0x5d
#define XPAR_IPI_PSM_IPI_TARGET_COUNT 0x10
#define XPAR_IPI_PSM_0_IPI_BITMASK 0x4
#define XPAR_IPI_PSM_0_IPI_BUF_INDEX 0x2
#define XPAR_IPI_PSM_1_IPI_BITMASK 0x8
#define XPAR_IPI_PSM_1_IPI_BUF_INDEX 0x3
#define XPAR_IPI_PSM_2_IPI_BITMASK 0x10
#define XPAR_IPI_PSM_2_IPI_BUF_INDEX 0x4
#define XPAR_IPI_PSM_3_IPI_BITMASK 0x20
#define XPAR_IPI_PSM_3_IPI_BUF_INDEX 0x5
#define XPAR_IPI_PSM_4_IPI_BITMASK 0x40
#define XPAR_IPI_PSM_4_IPI_BUF_INDEX 0x6
#define XPAR_IPI_PSM_5_IPI_BITMASK 0x80
#define XPAR_IPI_PSM_5_IPI_BUF_INDEX 0x7
#define XPAR_IPI_PSM_6_IPI_BITMASK 0x200
#define XPAR_IPI_PSM_6_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_7_IPI_BITMASK 0x400
#define XPAR_IPI_PSM_7_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_8_IPI_BITMASK 0x800
#define XPAR_IPI_PSM_8_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_9_IPI_BITMASK 0x1000
#define XPAR_IPI_PSM_9_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_10_IPI_BITMASK 0x2000
#define XPAR_IPI_PSM_10_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_11_IPI_BITMASK 0x4000
#define XPAR_IPI_PSM_11_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_12_IPI_BITMASK 0x8000
#define XPAR_IPI_PSM_12_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_13_IPI_BITMASK 0x2
#define XPAR_IPI_PSM_13_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PSM_14_IPI_BITMASK 0x100
#define XPAR_IPI_PSM_14_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PSM_15_IPI_BITMASK 0x1
#define XPAR_IPI_PSM_15_IPI_BUF_INDEX 0x0

/* Canonical definitions for peripheral IPI_PSM */
#define XPAR_XIPIPSU_0_BASEADDR 0xeb310000
#define XPAR_XIPIPSU_0_HIGHADDR 0xeb31ffff
#define XPAR_XIPIPSU_0_INTR 0x5d
#define XPAR_XIPIPSU_0_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_XIPIPSU_0_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_0_IPI_BUF_INDEX 0x0
#define XPAR_XIPIPSU_0_INTERRUPTS 0x403d
#define XPAR_XIPIPSU_0_IPI_TARGET_COUNT 0x10
#define XPAR_XIPIPSU_0_CH0_IPI_BITMASK 0x4
#define XPAR_XIPIPSU_0_CH0_IPI_BUF_INDEX 0x2
#define XPAR_XIPIPSU_0_CH1_IPI_BITMASK 0x8
#define XPAR_XIPIPSU_0_CH1_IPI_BUF_INDEX 0x3
#define XPAR_XIPIPSU_0_CH2_IPI_BITMASK 0x10
#define XPAR_XIPIPSU_0_CH2_IPI_BUF_INDEX 0x4
#define XPAR_XIPIPSU_0_CH3_IPI_BITMASK 0x20
#define XPAR_XIPIPSU_0_CH3_IPI_BUF_INDEX 0x5
#define XPAR_XIPIPSU_0_CH4_IPI_BITMASK 0x40
#define XPAR_XIPIPSU_0_CH4_IPI_BUF_INDEX 0x6
#define XPAR_XIPIPSU_0_CH5_IPI_BITMASK 0x80
#define XPAR_XIPIPSU_0_CH5_IPI_BUF_INDEX 0x7
#define XPAR_XIPIPSU_0_CH6_IPI_BITMASK 0x200
#define XPAR_XIPIPSU_0_CH6_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH7_IPI_BITMASK 0x400
#define XPAR_XIPIPSU_0_CH7_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH8_IPI_BITMASK 0x800
#define XPAR_XIPIPSU_0_CH8_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH9_IPI_BITMASK 0x1000
#define XPAR_XIPIPSU_0_CH9_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH10_IPI_BITMASK 0x2000
#define XPAR_XIPIPSU_0_CH10_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH11_IPI_BITMASK 0x4000
#define XPAR_XIPIPSU_0_CH11_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH12_IPI_BITMASK 0x8000
#define XPAR_XIPIPSU_0_CH12_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH13_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_0_CH13_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_0_CH14_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_0_CH14_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH15_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_0_CH15_IPI_BUF_INDEX 0x0

#define XPAR_XQSPIPSU_NUM_INSTANCES 1

/* Definitions for peripheral QSPI */
#define XPAR_QSPI_COMPATIBLE "xlnx,versal-qspi-1.0"
#define XPAR_QSPI_BASEADDR 0xf1030000
#define XPAR_QSPI_HIGHADDR 0xf1030fff
#define XPAR_QSPI_CLOCK_FREQ 0x11e19751
#define XPAR_QSPI_CONNECTION_MODE 0x2
#define XPAR_QSPI_BUS_WIDTH 0x2
#define XPAR_QSPI_INTERRUPTS 0x40b7
#define XPAR_QSPI_CLOCKS 0x39

/* Canonical definitions for peripheral QSPI */
#define XPAR_XQSPIPSU_0_BASEADDR 0xf1030000
#define XPAR_XQSPIPSU_0_HIGHADDR 0xf1030fff
#define XPAR_XQSPIPSU_0_BUS_WIDTH 0x2
#define XPAR_XQSPIPSU_0_COMPATIBLE "xlnx,versal-qspi-1.0"
#define XPAR_XQSPIPSU_0_CLOCK_FREQ 0x11e19751
#define XPAR_XQSPIPSU_0_CONNECTION_MODE 0x2
#define XPAR_XQSPIPSU_0_CLOCKS 0x39
#define XPAR_XQSPIPSU_0_INTERRUPTS 0x40b7

#define XPAR_XRTCPSU_NUM_INSTANCES 1

/* Definitions for peripheral RTC */
#define XPAR_RTC_COMPATIBLE "xlnx,zynqmp-rtc"
#define XPAR_RTC_BASEADDR 0xf12a0000
#define XPAR_RTC_HIGHADDR 0xf12a00ff
#define XPAR_RTC_INTERRUPTS 0x40c8
#define XPAR_RTC_INTERRUPTS_1 0x40c9

/* Canonical definitions for peripheral RTC */
#define XPAR_XRTCPSU_0_BASEADDR 0xf12a0000
#define XPAR_XRTCPSU_0_HIGHADDR 0xf12a00ff
#define XPAR_XRTCPSU_0_COMPATIBLE "xlnx,zynqmp-rtc"
#define XPAR_XRTCPSU_0_INTERRUPTS 0x40c8

#define XPAR_XSDPS_NUM_INSTANCES 1

/* Definitions for peripheral SDHCI0 */
#define XPAR_SDHCI0_COMPATIBLE "xlnx,versal-8.9a"
#define XPAR_SDHCI0_BASEADDR 0xf1040000
#define XPAR_SDHCI0_HIGHADDR 0xf104ffff
#define XPAR_SDHCI0_SDIO_CLK_FREQ_HZ 0xbebba31
#define XPAR_SDHCI0_HAS_CD 0x1
#define XPAR_SDHCI0_HAS_WP 0x1
#define XPAR_SDHCI0_BUS_WIDTH 0x8
#define XPAR_SDHCI0_MIO_BANK 0x0
#define XPAR_SDHCI0_HAS_EMIO 0x0
#define XPAR_SDHCI0_SLOT_TYPE 0x3
#define XPAR_SDHCI0_IS_CACHE_COHERENT 0x0
#define XPAR_SDHCI0_CLOCKS 0x3b
#define XPAR_SDHCI0_CLK_50_SDR_ITAP_DLY 0x0
#define XPAR_SDHCI0_CLK_50_SDR_OTAP_DLY 0x0
#define XPAR_SDHCI0_CLK_50_DDR_ITAP_DLY 0x0
#define XPAR_SDHCI0_CLK_50_DDR_OTAP_DLY 0x0
#define XPAR_SDHCI0_CLK_100_SDR_OTAP_DLY 0x0
#define XPAR_SDHCI0_CLK_200_SDR_OTAP_DLY 0x0

/* Canonical definitions for peripheral SDHCI0 */
#define XPAR_XSDPS_0_BASEADDR 0xf1040000
#define XPAR_XSDPS_0_HIGHADDR 0xf104ffff
#define XPAR_XSDPS_0_BUS_WIDTH 0x8
#define XPAR_XSDPS_0_COMPATIBLE "xlnx,versal-8.9a"
#define XPAR_XSDPS_0_CLOCKS 0x3b
#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0x0
#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0x0
#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0x0
#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0x0
#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0x0
#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0x0
#define XPAR_XSDPS_0_HAS_CD 0x1
#define XPAR_XSDPS_0_HAS_WP 0x1
#define XPAR_XSDPS_0_HAS_EMIO 0x0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0x0
#define XPAR_XSDPS_0_MIO_BANK 0x0
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 0xbebba31
#define XPAR_XSDPS_0_SLOT_TYPE 0x3

#define XPAR_XSYSMONPSV_NUM_INSTANCES 1

/* Definitions for peripheral SYSMON0 */
#define XPAR_SYSMON0_COMPATIBLE "xlnx,versal-sysmon"
#define XPAR_SYSMON0_BASEADDR 0xf1270000
#define XPAR_SYSMON0_HIGHADDR 0xf1273fff

/* Canonical definitions for peripheral SYSMON0 */
#define XPAR_XSYSMONPSV_0_BASEADDR 0xf1270000
#define XPAR_XSYSMONPSV_0_HIGHADDR 0xf1273fff
#define XPAR_XSYSMONPSV_0_COMPATIBLE "xlnx,versal-sysmon"

#define XPAR_XTRNGPSX_NUM_INSTANCES 1

/* Definitions for peripheral TRNG */
#define XPAR_TRNG_COMPATIBLE "xlnx,psx-pmc-trng-11.0"
#define XPAR_TRNG_BASEADDR 0xf1230000
#define XPAR_TRNG_HIGHADDR 0xf123ffff

/* Canonical definitions for peripheral TRNG */
#define XPAR_XTRNGPSX_0_BASEADDR 0xf1230000
#define XPAR_XTRNGPSX_0_HIGHADDR 0xf123ffff
#define XPAR_XTRNGPSX_0_COMPATIBLE "xlnx,psx-pmc-trng-11.0"

#define XPAR_XTTCPS_NUM_INSTANCES 4

/* Definitions for peripheral TTC0 */
#define XPAR_TTC0_COMPATIBLE "cdns,ttc"
#define XPAR_TTC0_BASEADDR 0xf1dc0000
#define XPAR_TTC0_HIGHADDR 0xf1dc0fff
#define XPAR_TTC0_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC0_INTERRUPTS 0x402b
#define XPAR_TTC0_INTERRUPTS_1 0x402c
#define XPAR_TTC0_INTERRUPTS_2 0x402d
#define XPAR_TTC0_TTC_CLK0_CLKSRC 0x1

/* Canonical definitions for peripheral TTC0 */
#define XPAR_XTTCPS_0_BASEADDR 0xf1dc0000
#define XPAR_XTTCPS_0_HIGHADDR 0xf1dc0fff
#define XPAR_XTTCPS_0_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_0_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_0_INTERRUPTS 0x402b
#define XPAR_XTTCPS_0_TTC_CLK0_CLKSRC 0x1

/* Definitions for peripheral TTC1 */
#define XPAR_TTC1_COMPATIBLE "cdns,ttc"
#define XPAR_TTC1_BASEADDR 0xf1dd0000
#define XPAR_TTC1_HIGHADDR 0xf1dd0fff
#define XPAR_TTC1_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC1_INTERRUPTS 0x402e
#define XPAR_TTC1_INTERRUPTS_1 0x402f
#define XPAR_TTC1_INTERRUPTS_2 0x4030
#define XPAR_TTC1_TTC_CLK0_CLKSRC 0x1

/* Canonical definitions for peripheral TTC1 */
#define XPAR_XTTCPS_1_BASEADDR 0xf1dd0000
#define XPAR_XTTCPS_1_HIGHADDR 0xf1dd0fff
#define XPAR_XTTCPS_1_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_1_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_1_INTERRUPTS 0x402e
#define XPAR_XTTCPS_1_TTC_CLK0_CLKSRC 0x1

/* Definitions for peripheral TTC2 */
#define XPAR_TTC2_COMPATIBLE "cdns,ttc"
#define XPAR_TTC2_BASEADDR 0xf1de0000
#define XPAR_TTC2_HIGHADDR 0xf1de0fff
#define XPAR_TTC2_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC2_INTERRUPTS 0x4031
#define XPAR_TTC2_INTERRUPTS_1 0x4032
#define XPAR_TTC2_INTERRUPTS_2 0x4033
#define XPAR_TTC2_TTC_CLK0_CLKSRC 0x1

/* Canonical definitions for peripheral TTC2 */
#define XPAR_XTTCPS_2_BASEADDR 0xf1de0000
#define XPAR_XTTCPS_2_HIGHADDR 0xf1de0fff
#define XPAR_XTTCPS_2_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_2_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_2_INTERRUPTS 0x4031
#define XPAR_XTTCPS_2_TTC_CLK0_CLKSRC 0x1

/* Definitions for peripheral TTC3 */
#define XPAR_TTC3_COMPATIBLE "cdns,ttc"
#define XPAR_TTC3_BASEADDR 0xf1df0000
#define XPAR_TTC3_HIGHADDR 0xf1df0fff
#define XPAR_TTC3_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC3_INTERRUPTS 0x4034
#define XPAR_TTC3_INTERRUPTS_1 0x4035
#define XPAR_TTC3_INTERRUPTS_2 0x4036
#define XPAR_TTC3_TTC_CLK0_CLKSRC 0x1

/* Canonical definitions for peripheral TTC3 */
#define XPAR_XTTCPS_3_BASEADDR 0xf1df0000
#define XPAR_XTTCPS_3_HIGHADDR 0xf1df0fff
#define XPAR_XTTCPS_3_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_3_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_3_INTERRUPTS 0x4034
#define XPAR_XTTCPS_3_TTC_CLK0_CLKSRC 0x1

#define XPAR_XUARTPSV_NUM_INSTANCES 2

/* Definitions for peripheral SERIAL0 */
#define XPAR_SERIAL0_COMPATIBLE "arm,pl011"
#define XPAR_SERIAL0_BASEADDR 0xf1920000
#define XPAR_SERIAL0_HIGHADDR 0xf1920fff
#define XPAR_SERIAL0_CLOCK_FREQ 0x5f5dd19
#define XPAR_SERIAL0_BAUDRATE 0x1c200
#define XPAR_SERIAL0_INTERRUPTS 0x4019

/* Canonical definitions for peripheral SERIAL0 */
#define XPAR_XUARTPSV_0_BASEADDR 0xf1920000
#define XPAR_XUARTPSV_0_HIGHADDR 0xf1920fff
#define XPAR_XUARTPSV_0_BAUDRATE 0x1c200
#define XPAR_XUARTPSV_0_COMPATIBLE "arm,pl011"
#define XPAR_XUARTPSV_0_CLOCK_FREQ 0x5f5dd19
#define XPAR_XUARTPSV_0_INTERRUPTS 0x4019

/* Definitions for peripheral SERIAL1 */
#define XPAR_SERIAL1_COMPATIBLE "arm,pl011"
#define XPAR_SERIAL1_BASEADDR 0xf1930000
#define XPAR_SERIAL1_HIGHADDR 0xf1930fff
#define XPAR_SERIAL1_CLOCK_FREQ 0x5f5dd19
#define XPAR_SERIAL1_BAUDRATE 0x1c200
#define XPAR_SERIAL1_INTERRUPTS 0x401a

/* Canonical definitions for peripheral SERIAL1 */
#define XPAR_XUARTPSV_1_BASEADDR 0xf1930000
#define XPAR_XUARTPSV_1_HIGHADDR 0xf1930fff
#define XPAR_XUARTPSV_1_BAUDRATE 0x1c200
#define XPAR_XUARTPSV_1_COMPATIBLE "arm,pl011"
#define XPAR_XUARTPSV_1_CLOCK_FREQ 0x5f5dd19
#define XPAR_XUARTPSV_1_INTERRUPTS 0x401a

#define XPAR_XUSBPSU_NUM_INSTANCES 1

/* Definitions for peripheral DWC3_1 */
#define XPAR_DWC3_1_COMPATIBLE "snps,dwc3"
#define XPAR_DWC3_1_BASEADDR 0xf1c00000
#define XPAR_DWC3_1_HIGHADDR 0xf1c0ffff

/* Canonical definitions for peripheral DWC3_1 */
#define XPAR_XUSBPSU_0_BASEADDR 0xf1c00000
#define XPAR_XUSBPSU_0_HIGHADDR 0xf1c0ffff
#define XPAR_XUSBPSU_0_COMPATIBLE "snps,dwc3"

#define XPAR_XZDMA_NUM_INSTANCES 8

/* Definitions for peripheral ADMA0 */
#define XPAR_ADMA0_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA0_BASEADDR 0xebd00000
#define XPAR_ADMA0_HIGHADDR 0xebd00fff
#define XPAR_ADMA0_DMA_MODE 0x1
#define XPAR_ADMA0_INTERRUPTS 0x4048

/* Canonical definitions for peripheral ADMA0 */
#define XPAR_XZDMA_0_BASEADDR 0xebd00000
#define XPAR_XZDMA_0_HIGHADDR 0xebd00fff
#define XPAR_XZDMA_0_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_0_DMA_MODE 0x1
#define XPAR_XZDMA_0_INTERRUPTS 0x4048

/* Definitions for peripheral ADMA1 */
#define XPAR_ADMA1_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA1_BASEADDR 0xebd10000
#define XPAR_ADMA1_HIGHADDR 0xebd10fff
#define XPAR_ADMA1_DMA_MODE 0x1
#define XPAR_ADMA1_INTERRUPTS 0x4049

/* Canonical definitions for peripheral ADMA1 */
#define XPAR_XZDMA_1_BASEADDR 0xebd10000
#define XPAR_XZDMA_1_HIGHADDR 0xebd10fff
#define XPAR_XZDMA_1_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_1_DMA_MODE 0x1
#define XPAR_XZDMA_1_INTERRUPTS 0x4049

/* Definitions for peripheral ADMA2 */
#define XPAR_ADMA2_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA2_BASEADDR 0xebd20000
#define XPAR_ADMA2_HIGHADDR 0xebd20fff
#define XPAR_ADMA2_DMA_MODE 0x1
#define XPAR_ADMA2_INTERRUPTS 0x404a

/* Canonical definitions for peripheral ADMA2 */
#define XPAR_XZDMA_2_BASEADDR 0xebd20000
#define XPAR_XZDMA_2_HIGHADDR 0xebd20fff
#define XPAR_XZDMA_2_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_2_DMA_MODE 0x1
#define XPAR_XZDMA_2_INTERRUPTS 0x404a

/* Definitions for peripheral ADMA3 */
#define XPAR_ADMA3_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA3_BASEADDR 0xebd30000
#define XPAR_ADMA3_HIGHADDR 0xebd30fff
#define XPAR_ADMA3_DMA_MODE 0x1
#define XPAR_ADMA3_INTERRUPTS 0x404b

/* Canonical definitions for peripheral ADMA3 */
#define XPAR_XZDMA_3_BASEADDR 0xebd30000
#define XPAR_XZDMA_3_HIGHADDR 0xebd30fff
#define XPAR_XZDMA_3_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_3_DMA_MODE 0x1
#define XPAR_XZDMA_3_INTERRUPTS 0x404b

/* Definitions for peripheral ADMA4 */
#define XPAR_ADMA4_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA4_BASEADDR 0xebd40000
#define XPAR_ADMA4_HIGHADDR 0xebd40fff
#define XPAR_ADMA4_DMA_MODE 0x1
#define XPAR_ADMA4_INTERRUPTS 0x404c

/* Canonical definitions for peripheral ADMA4 */
#define XPAR_XZDMA_4_BASEADDR 0xebd40000
#define XPAR_XZDMA_4_HIGHADDR 0xebd40fff
#define XPAR_XZDMA_4_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_4_DMA_MODE 0x1
#define XPAR_XZDMA_4_INTERRUPTS 0x404c

/* Definitions for peripheral ADMA5 */
#define XPAR_ADMA5_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA5_BASEADDR 0xebd50000
#define XPAR_ADMA5_HIGHADDR 0xebd50fff
#define XPAR_ADMA5_DMA_MODE 0x1
#define XPAR_ADMA5_INTERRUPTS 0x404d

/* Canonical definitions for peripheral ADMA5 */
#define XPAR_XZDMA_5_BASEADDR 0xebd50000
#define XPAR_XZDMA_5_HIGHADDR 0xebd50fff
#define XPAR_XZDMA_5_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_5_DMA_MODE 0x1
#define XPAR_XZDMA_5_INTERRUPTS 0x404d

/* Definitions for peripheral ADMA6 */
#define XPAR_ADMA6_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA6_BASEADDR 0xebd60000
#define XPAR_ADMA6_HIGHADDR 0xebd60fff
#define XPAR_ADMA6_DMA_MODE 0x1
#define XPAR_ADMA6_INTERRUPTS 0x404e

/* Canonical definitions for peripheral ADMA6 */
#define XPAR_XZDMA_6_BASEADDR 0xebd60000
#define XPAR_XZDMA_6_HIGHADDR 0xebd60fff
#define XPAR_XZDMA_6_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_6_DMA_MODE 0x1
#define XPAR_XZDMA_6_INTERRUPTS 0x404e

/* Definitions for peripheral ADMA7 */
#define XPAR_ADMA7_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_ADMA7_BASEADDR 0xebd70000
#define XPAR_ADMA7_HIGHADDR 0xebd70fff
#define XPAR_ADMA7_DMA_MODE 0x1
#define XPAR_ADMA7_INTERRUPTS 0x404f

/* Canonical definitions for peripheral ADMA7 */
#define XPAR_XZDMA_7_BASEADDR 0xebd70000
#define XPAR_XZDMA_7_HIGHADDR 0xebd70fff
#define XPAR_XZDMA_7_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_7_DMA_MODE 0x1
#define XPAR_XZDMA_7_INTERRUPTS 0x404f

/* Definitions for peripheral USB1 */
#define XPAR_USB1_BASEADDR 0xf1e10000
#define XPAR_USB1_HIGHADDR 0xf1e100ff

/* Canonical definitions for peripheral USB1 */
#define XPAR_PSX_USB_0_BASEADDR 0xf1e10000
#define XPAR_PSX_USB_0_HIGHADDR 0xf1e100ff

/* Definitions for peripheral PMC_PPU1_MDM_0 */
#define XPAR_PMC_PPU1_MDM_0_BASEADDR 0xf0310000
#define XPAR_PMC_PPU1_MDM_0_HIGHADDR 0xf0317fff

/* Canonical definitions for peripheral PMC_PPU1_MDM_0 */
#define XPAR_PSX_PMC_PPU1_MDM_0_BASEADDR 0xf0310000
#define XPAR_PSX_PMC_PPU1_MDM_0_HIGHADDR 0xf0317fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_AES */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_AES_BASEADDR 0xf11e0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_AES_HIGHADDR 0xf11effff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_AES */
#define XPAR_PSX_PMC_AES_0_BASEADDR 0xf11e0000
#define XPAR_PSX_PMC_AES_0_HIGHADDR 0xf11effff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_BBRAM_CTRL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_BBRAM_CTRL_BASEADDR 0xf11f0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_BBRAM_CTRL_HIGHADDR 0xf11fffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_BBRAM_CTRL */
#define XPAR_PSX_PMC_BBRAM_CTRL_0_BASEADDR 0xf11f0000
#define XPAR_PSX_PMC_BBRAM_CTRL_0_HIGHADDR 0xf11fffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CPM */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CPM_BASEADDR 0xe4000000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CPM_HIGHADDR 0xe4ffffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CPM */
#define XPAR_PSX_CPM_0_BASEADDR 0xe4000000
#define XPAR_PSX_CPM_0_HIGHADDR 0xe4ffffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CRF_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CRF_0_BASEADDR 0xec200000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CRF_0_HIGHADDR 0xec2fffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CRF_0 */
#define XPAR_PSX_CRF_0_BASEADDR 0xec200000
#define XPAR_PSX_CRF_0_HIGHADDR 0xec2fffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CRL_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CRL_0_BASEADDR 0xeb5e0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CRL_0_HIGHADDR 0xeb8dffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CRL_0 */
#define XPAR_PSX_CRL_0_BASEADDR 0xeb5e0000
#define XPAR_PSX_CRL_0_HIGHADDR 0xeb8dffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CRP_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CRP_0_BASEADDR 0xf1260000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_CRP_0_HIGHADDR 0xf126ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_CRP_0 */
#define XPAR_PSX_CRP_0_BASEADDR 0xf1260000
#define XPAR_PSX_CRP_0_HIGHADDR 0xf126ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_RSA */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_RSA_BASEADDR 0xf1200000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_RSA_HIGHADDR 0xf120ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_RSA */
#define XPAR_PSX_PMC_RSA_0_BASEADDR 0xf1200000
#define XPAR_PSX_PMC_RSA_0_HIGHADDR 0xf120ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CACHE */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CACHE_BASEADDR 0xf1250000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CACHE_HIGHADDR 0xf125ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CACHE */
#define XPAR_PSX_PMC_EFUSE_CACHE_0_BASEADDR 0xf1250000
#define XPAR_PSX_PMC_EFUSE_CACHE_0_HIGHADDR 0xf125ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CTRL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CTRL_BASEADDR 0xf1240000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CTRL_HIGHADDR 0xf124ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_EFUSE_CTRL */
#define XPAR_PSX_PMC_EFUSE_CTRL_0_BASEADDR 0xf1240000
#define XPAR_PSX_PMC_EFUSE_CTRL_0_HIGHADDR 0xf124ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_0_BASEADDR 0xec880000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_0_HIGHADDR 0xec88ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_0 */
#define XPAR_PSX_FPD_AFI_0_BASEADDR 0xec880000
#define XPAR_PSX_FPD_AFI_0_HIGHADDR 0xec88ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_1 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_1_BASEADDR 0xec890000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_1_HIGHADDR 0xec89ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_1 */
#define XPAR_PSX_FPD_AFI_1_BASEADDR 0xec890000
#define XPAR_PSX_FPD_AFI_1_HIGHADDR 0xec89ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_2 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_2_BASEADDR 0xec8a0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_2_HIGHADDR 0xec8affff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_2 */
#define XPAR_PSX_FPD_AFI_2_BASEADDR 0xec8a0000
#define XPAR_PSX_FPD_AFI_2_HIGHADDR 0xec8affff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_3 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_3_BASEADDR 0xec8b0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_3_HIGHADDR 0xec8bffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_AFI_3 */
#define XPAR_PSX_FPD_AFI_3_BASEADDR 0xec8b0000
#define XPAR_PSX_FPD_AFI_3_HIGHADDR 0xec8bffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_CMN */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_CMN_BASEADDR 0xf8000000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_CMN_HIGHADDR 0xfbffffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_CMN */
#define XPAR_PSX_FPD_CMN_0_BASEADDR 0xf8000000
#define XPAR_PSX_FPD_CMN_0_HIGHADDR 0xfbffffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_GPV_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_GPV_0_BASEADDR 0xec800000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_GPV_0_HIGHADDR 0xec803fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_GPV_0 */
#define XPAR_PSX_FPD_GPV_0_BASEADDR 0xec800000
#define XPAR_PSX_FPD_GPV_0_HIGHADDR 0xec803fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SLAVE_XMPU_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SLAVE_XMPU_0_BASEADDR 0xec810000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SLAVE_XMPU_0_HIGHADDR 0xec81ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SLAVE_XMPU_0 */
#define XPAR_PSX_FPD_SLAVE_XMPU_0_BASEADDR 0xec810000
#define XPAR_PSX_FPD_SLAVE_XMPU_0_HIGHADDR 0xec81ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_0_BASEADDR 0xec8c0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_0_HIGHADDR 0xec8cffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_0 */
#define XPAR_PSX_FPD_SLCR_0_BASEADDR 0xec8c0000
#define XPAR_PSX_FPD_SLCR_0_HIGHADDR 0xec8cffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_SECURE_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_SECURE_0_BASEADDR 0xec8e0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_SECURE_0_HIGHADDR 0xec8effff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SLCR_SECURE_0 */
#define XPAR_PSX_FPD_SLCR_SECURE_0_BASEADDR 0xec8e0000
#define XPAR_PSX_FPD_SLCR_SECURE_0_HIGHADDR 0xec8effff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_CTRL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_CTRL_BASEADDR 0xec920000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_CTRL_HIGHADDR 0xec92ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_CTRL */
#define XPAR_PSX_FPD_SYSTMR_CTRL_0_BASEADDR 0xec920000
#define XPAR_PSX_FPD_SYSTMR_CTRL_0_HIGHADDR 0xec92ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_READ */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_READ_BASEADDR 0xec910000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_READ_HIGHADDR 0xec91ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_FPD_SYSTMR_READ */
#define XPAR_PSX_FPD_SYSTMR_READ_0_BASEADDR 0xec910000
#define XPAR_PSX_FPD_SYSTMR_READ_0_HIGHADDR 0xec91ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_AFI_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_AFI_0_BASEADDR 0xeb9b0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_AFI_0_HIGHADDR 0xeb9bffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_AFI_0 */
#define XPAR_PSX_LPD_AFI_0_BASEADDR 0xeb9b0000
#define XPAR_PSX_LPD_AFI_0_HIGHADDR 0xeb9bffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SECURE_SLCR_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SECURE_SLCR_0_BASEADDR 0xf19c0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SECURE_SLCR_0_HIGHADDR 0xf19cffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SECURE_SLCR_0 */
#define XPAR_PSX_LPD_IOU_SECURE_SLCR_0_BASEADDR 0xf19c0000
#define XPAR_PSX_LPD_IOU_SECURE_SLCR_0_HIGHADDR 0xf19cffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SLCR_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SLCR_0_BASEADDR 0xf19a0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SLCR_0_HIGHADDR 0xf19bffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_IOU_SLCR_0 */
#define XPAR_PSX_LPD_IOU_SLCR_0_BASEADDR 0xf19a0000
#define XPAR_PSX_LPD_IOU_SLCR_0_HIGHADDR 0xf19bffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_0_BASEADDR 0xeb410000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_0_HIGHADDR 0xeb50ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_0 */
#define XPAR_PSX_LPD_SLCR_0_BASEADDR 0xeb410000
#define XPAR_PSX_LPD_SLCR_0_HIGHADDR 0xeb50ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_SECURE_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_SECURE_0_BASEADDR 0xeb510000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_SECURE_0_HIGHADDR 0xeb54ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SLCR_SECURE_0 */
#define XPAR_PSX_LPD_SLCR_SECURE_0_BASEADDR 0xeb510000
#define XPAR_PSX_LPD_SLCR_SECURE_0_HIGHADDR 0xeb54ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_CTRL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_CTRL_BASEADDR 0xeb5b0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_CTRL_HIGHADDR 0xeb5bffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_CTRL */
#define XPAR_PSX_LPD_SYSTMR_CTRL_0_BASEADDR 0xeb5b0000
#define XPAR_PSX_LPD_SYSTMR_CTRL_0_HIGHADDR 0xeb5bffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_READ */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_READ_BASEADDR 0xeb5a0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_READ_HIGHADDR 0xeb5affff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_SYSTMR_READ */
#define XPAR_PSX_LPD_SYSTMR_READ_0_BASEADDR 0xeb5a0000
#define XPAR_PSX_LPD_SYSTMR_READ_0_HIGHADDR 0xeb5affff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_XPPU_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_XPPU_0_BASEADDR 0xeb990000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_LPD_XPPU_0_HIGHADDR 0xeb99ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_LPD_XPPU_0 */
#define XPAR_PSX_LPD_XPPU_0_BASEADDR 0xeb990000
#define XPAR_PSX_LPD_XPPU_0_HIGHADDR 0xeb99ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_0_BASEADDR 0xeb5d0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_0_HIGHADDR 0xeb5dffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_0 */
#define XPAR_PSX_OCM_0_BASEADDR 0xeb5d0000
#define XPAR_PSX_OCM_0_HIGHADDR 0xeb5dffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_0_BASEADDR 0xeb400000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_0_HIGHADDR 0xeb40ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_0 */
#define XPAR_PSX_OCM_XMPU_0_BASEADDR 0xeb400000
#define XPAR_PSX_OCM_XMPU_0_HIGHADDR 0xeb40ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_1 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_1_BASEADDR 0xeb960000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_1_HIGHADDR 0xeb96ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_CTRL_1 */
#define XPAR_PSX_OCM_1_BASEADDR 0xeb960000
#define XPAR_PSX_OCM_1_HIGHADDR 0xeb96ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_1 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_1_BASEADDR 0xeb980000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_1_HIGHADDR 0xeb98ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_OCM_XMPU_1 */
#define XPAR_PSX_OCM_XMPU_1_BASEADDR 0xeb980000
#define XPAR_PSX_OCM_XMPU_1_HIGHADDR 0xeb98ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_GLOBAL_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_GLOBAL_0_BASEADDR 0xf1110000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_GLOBAL_0_HIGHADDR 0xf115ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_GLOBAL_0 */
#define XPAR_PSX_PMC_GLOBAL_0_BASEADDR 0xf1110000
#define XPAR_PSX_PMC_GLOBAL_0_HIGHADDR 0xf115ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_RAM_NPI */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_RAM_NPI_BASEADDR 0xf6000000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_RAM_NPI_HIGHADDR 0xf7ffffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_RAM_NPI */
#define XPAR_PSX_PMC_RAM_NPI_0_BASEADDR 0xf6000000
#define XPAR_PSX_PMC_RAM_NPI_0_HIGHADDR 0xf7ffffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT_BASEADDR 0xf1220000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT_HIGHADDR 0xf122ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT */
#define XPAR_PSX_PMC_SLAVE_BOOT_0_BASEADDR 0xf1220000
#define XPAR_PSX_PMC_SLAVE_BOOT_0_HIGHADDR 0xf122ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT_STREAM */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT_STREAM_BASEADDR 0xf2100000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT_STREAM_HIGHADDR 0xf210ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_SLAVE_BOOT_STREAM */
#define XPAR_PSX_PMC_SLAVE_BOOT_STREAM_0_BASEADDR 0xf2100000
#define XPAR_PSX_PMC_SLAVE_BOOT_STREAM_0_HIGHADDR 0xf210ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_XMPU_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_XMPU_0_BASEADDR 0xf12f0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_XMPU_0_HIGHADDR 0xf12fffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_XMPU_0 */
#define XPAR_PSX_PMC_XMPU_0_BASEADDR 0xf12f0000
#define XPAR_PSX_PMC_XMPU_0_HIGHADDR 0xf12fffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_0_BASEADDR 0xf1310000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_0_HIGHADDR 0xf131ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_0 */
#define XPAR_PSX_PMC_XPPU_0_BASEADDR 0xf1310000
#define XPAR_PSX_PMC_XPPU_0_HIGHADDR 0xf131ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_NPI_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_NPI_0_BASEADDR 0xf1300000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_NPI_0_HIGHADDR 0xf130ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_XPPU_NPI_0 */
#define XPAR_PSX_PMC_XPPU_NPI_0_BASEADDR 0xf1300000
#define XPAR_PSX_PMC_XPPU_NPI_0_HIGHADDR 0xf130ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_GLOBAL_REG */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_GLOBAL_REG_BASEADDR 0xebc90000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_GLOBAL_REG_HIGHADDR 0xebc9efff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_GLOBAL_REG */
#define XPAR_PSX_PSM_GLOBAL_REG_0_BASEADDR 0xebc90000
#define XPAR_PSX_PSM_GLOBAL_REG_0_HIGHADDR 0xebc9efff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_INJECT_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_INJECT_0_BASEADDR 0xebcd0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_INJECT_0_HIGHADDR 0xebcdffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_INJECT_0 */
#define XPAR_PSX_TMR_INJECT_0_BASEADDR 0xebcd0000
#define XPAR_PSX_TMR_INJECT_0_HIGHADDR 0xebcdffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_MANAGER_0 */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_MANAGER_0_BASEADDR 0xebcc0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_MANAGER_0_HIGHADDR 0xebccffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_TMR_MANAGER_0 */
#define XPAR_PSX_TMR_MANAGER_0_BASEADDR 0xebcc0000
#define XPAR_PSX_TMR_MANAGER_0_HIGHADDR 0xebccffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0A_ATCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0A_ATCM_GLOBAL_BASEADDR 0xeba00000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0A_ATCM_GLOBAL_HIGHADDR 0xeba0ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0A_ATCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_0_BASEADDR 0xeba00000
#define XPAR_PSX_TCM_GLOBAL_0_HIGHADDR 0xeba0ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0A_BTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0A_BTCM_GLOBAL_BASEADDR 0xeba10000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0A_BTCM_GLOBAL_HIGHADDR 0xeba17fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0A_BTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_1_BASEADDR 0xeba10000
#define XPAR_PSX_TCM_GLOBAL_1_HIGHADDR 0xeba17fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0A_CTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0A_CTCM_GLOBAL_BASEADDR 0xeba20000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0A_CTCM_GLOBAL_HIGHADDR 0xeba27fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0A_CTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_2_BASEADDR 0xeba20000
#define XPAR_PSX_TCM_GLOBAL_2_HIGHADDR 0xeba27fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0B_ATCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0B_ATCM_GLOBAL_BASEADDR 0xeba80000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0B_ATCM_GLOBAL_HIGHADDR 0xeba8ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0B_ATCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_3_BASEADDR 0xeba80000
#define XPAR_PSX_TCM_GLOBAL_3_HIGHADDR 0xeba8ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0B_BTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0B_BTCM_GLOBAL_BASEADDR 0xeba90000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0B_BTCM_GLOBAL_HIGHADDR 0xeba97fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0B_BTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_4_BASEADDR 0xeba90000
#define XPAR_PSX_TCM_GLOBAL_4_HIGHADDR 0xeba97fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0B_CTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0B_CTCM_GLOBAL_BASEADDR 0xebaa0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_0B_CTCM_GLOBAL_HIGHADDR 0xebaa7fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_0B_CTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_5_BASEADDR 0xebaa0000
#define XPAR_PSX_TCM_GLOBAL_5_HIGHADDR 0xebaa7fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1A_ATCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1A_ATCM_GLOBAL_BASEADDR 0xeba40000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1A_ATCM_GLOBAL_HIGHADDR 0xeba4ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1A_ATCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_6_BASEADDR 0xeba40000
#define XPAR_PSX_TCM_GLOBAL_6_HIGHADDR 0xeba4ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1A_BTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1A_BTCM_GLOBAL_BASEADDR 0xeba50000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1A_BTCM_GLOBAL_HIGHADDR 0xeba57fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1A_BTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_7_BASEADDR 0xeba50000
#define XPAR_PSX_TCM_GLOBAL_7_HIGHADDR 0xeba57fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1A_CTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1A_CTCM_GLOBAL_BASEADDR 0xeba60000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1A_CTCM_GLOBAL_HIGHADDR 0xeba67fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1A_CTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_8_BASEADDR 0xeba60000
#define XPAR_PSX_TCM_GLOBAL_8_HIGHADDR 0xeba67fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1B_ATCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1B_ATCM_GLOBAL_BASEADDR 0xebac0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1B_ATCM_GLOBAL_HIGHADDR 0xebacffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1B_ATCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_9_BASEADDR 0xebac0000
#define XPAR_PSX_TCM_GLOBAL_9_HIGHADDR 0xebacffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1B_BTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1B_BTCM_GLOBAL_BASEADDR 0xebad0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1B_BTCM_GLOBAL_HIGHADDR 0xebad7fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1B_BTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_10_BASEADDR 0xebad0000
#define XPAR_PSX_TCM_GLOBAL_10_HIGHADDR 0xebad7fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1B_CTCM_GLOBAL */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1B_CTCM_GLOBAL_BASEADDR 0xebae0000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_R52_1B_CTCM_GLOBAL_HIGHADDR 0xebae7fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_R52_1B_CTCM_GLOBAL */
#define XPAR_PSX_TCM_GLOBAL_11_BASEADDR 0xebae0000
#define XPAR_PSX_TCM_GLOBAL_11_HIGHADDR 0xebae7fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_DATA_CNTLR */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_DATA_CNTLR_BASEADDR 0xebc20000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_DATA_CNTLR_HIGHADDR 0xebc27fff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_DATA_CNTLR */
#define XPAR_PSX_PSM_PPU_0_BASEADDR 0xebc20000
#define XPAR_PSX_PSM_PPU_0_HIGHADDR 0xebc27fff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_INSTR_CNTLR */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_INSTR_CNTLR_BASEADDR 0xebc00000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_INSTR_CNTLR_HIGHADDR 0xebc1ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PSM_RAM_INSTR_CNTLR */
#define XPAR_PSX_RAM_INSTR_CNTLR_0_BASEADDR 0xebc00000
#define XPAR_PSX_RAM_INSTR_CNTLR_0_HIGHADDR 0xebc1ffff

/* Definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_SHA */
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_SHA_BASEADDR 0xf1210000
#define XPAR_PSX_WIZARD_0_PSXL_0_PSX_PMC_SHA_HIGHADDR 0xf121ffff

/* Canonical definitions for peripheral PSX_WIZARD_0_PSXL_0_PSX_PMC_SHA */
#define XPAR_PSX_PMC_SHA_0_BASEADDR 0xf1210000
#define XPAR_PSX_PMC_SHA_0_HIGHADDR 0xf121ffff

#define XPAR_AXI_NOC2_DDR_LOW_0_BASEADDR 0x0
#define XPAR_AXI_NOC2_DDR_LOW_0_HIGHADDR 0x7fffffff
#define XPAR_PSX_OCM_0_BASEADDRESS 0xbbf00000
#define XPAR_PSX_OCM_0_HIGHADDRESS 0xbbf7ffff
#define XPAR_PSX_OCM_1_BASEADDRESS 0xbbf80000
#define XPAR_PSX_OCM_1_HIGHADDRESS 0xbbffffff

/*  CPU parameters definition */
#define XPAR_PSX_PSM_UNALIGNED_EXCEPTIONS 1
#define XPAR_PSX_PSM_FPU_EXCEPTION 0
#define XPAR_PSX_PSM_FSL_EXCEPTION 0
#define XPAR_PSX_PSM_DIV_ZERO_EXCEPTION 1
#define XPAR_PSX_PSM_ILL_OPCODE_EXCEPTION 1
#define XPAR_PSX_PSM_USE_STACK_PROTECTION 1
#define XPAR_PSX_PSM_FREQ 100000000
#define XPAR_PSX_PSM_USE_MSR_INSTR 1
#define XPAR_PSX_PSM_D_CACHE_LINE_SIZE 16
#define XPAR_PSX_PSM_DCACHE_ALWAYS_USED 0
#define XPAR_PSX_PSM_D_CACHE_SIZE 8192
#define XPAR_PSX_PSM_I_CACHE_LINE_SIZE 16
#define XPAR_PSX_PSM_I_CACHE_SIZE 8192
#define XPAR_PSX_PSM_ADDR_TAG_BITS 0
#define XPAR_PSX_PSM_ALLOW_DCACHE_WR 1
#define XPAR_PSX_PSM_ALLOW_ICACHE_WR 1
#define XPAR_PSX_PSM_AREA_OPTIMIZED 0
#define XPAR_PSX_PSM_CACHE_BYTE_SIZE 8192
#define XPAR_PSX_PSM_D_LMB 1
#define XPAR_PSX_PSM_I_LMB 1
#define XPAR_PSX_PSM_DCACHE_ADDR_TAG 0
#define XPAR_PSX_PSM_DCACHE_BYTE_SIZE 8192
#define XPAR_PSX_PSM_DCACHE_LINE_LEN 4
#define XPAR_PSX_PSM_DCACHE_USE_WRITEBACK 0
#define XPAR_PSX_PSM_DEBUG_ENABLED 1
#define XPAR_PSX_PSM_DYNAMIC_BUS_SIZING 0
#define XPAR_PSX_PSM_EDGE_IS_POSITIVE 1
#define XPAR_PSX_PSM_ENDIANNESS 1
#define XPAR_PSX_PSM_FSL_LINKS 0
#define XPAR_PSX_PSM_ICACHE_ALWAYS_USED 0
#define XPAR_PSX_PSM_ICACHE_LINE_LEN 4
#define XPAR_PSX_PSM_INTERCONNECT 2
#define XPAR_PSX_PSM_INTERRUPT_IS_EDGE 0
#define XPAR_PSX_PSM_MMU_DTLB_SIZE 4
#define XPAR_PSX_PSM_MMU_ITLB_SIZE 2
#define XPAR_PSX_PSM_MMU_TLB_ACCESS 3
#define XPAR_PSX_PSM_MMU_ZONES 16
#define XPAR_PSX_PSM_NUMBER_OF_PC_BRK 2
#define XPAR_PSX_PSM_NUMBER_OF_RD_ADDR_BRK 1
#define XPAR_PSX_PSM_NUMBER_OF_WR_ADDR_BRK 1
#define XPAR_PSX_PSM_OPCODE_0X0_ILLEGAL 1
#define XPAR_PSX_PSM_PVR 2
#define XPAR_PSX_PSM_PVR_USER2 0
#define XPAR_PSX_PSM_RESET_MSR 0
#define XPAR_PSX_PSM_SCO 0
#define XPAR_PSX_PSM_USE_BARREL 1
#define XPAR_PSX_PSM_USE_DCACHE 0
#define XPAR_PSX_PSM_USE_DIV 1
#define XPAR_PSX_PSM_USE_EXT_BRK 0
#define XPAR_PSX_PSM_USE_EXT_NM_BRK 0
#define XPAR_PSX_PSM_USE_EXTENDED_FSL_INSTR 0
#define XPAR_PSX_PSM_USE_FPU 0
#define XPAR_PSX_PSM_USE_HW_MUL 2
#define XPAR_PSX_PSM_USE_ICACHE 0
#define XPAR_PSX_PSM_USE_INTERRUPT 1
#define XPAR_PSX_PSM_USE_MMU 0
#define XPAR_PSX_PSM_USE_PCMP_INSTR 1
#define XPAR_PSX_PSM_D_CACHE_BASEADDR 0
#define XPAR_PSX_PSM_D_CACHE_HIGHADDR 1073741823
#define XPAR_PSX_PSM_I_CACHE_BASEADDR 0
#define XPAR_PSX_PSM_I_CACHE_HIGHADDR 1073741823
#define XPAR_PSX_PSM_REG 1
#define XPAR_PSX_PSM_BASE_VECTORS 3955228672
#define XPAR_PSX_PSM_FAULT_TOLERANT 1

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 100000000

#define XPAR_MICROBLAZE_DDR_RESERVE_SA 0

#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000

/* Number of SLRs */
#define NUMBER_OF_SLRS 0x1

/* Device ID */
#define XPAR_DEVICE_ID "xcvn3716"

/* DDRMC5_I2C_MASTER */
#define DDRMC5_I2C_MASTER "PMC"

/* DDRMC5_DEBUG_ELF */
#define DDRMC5_DEBUG_ELF "false"

#endif  /* end of protection macro */