#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_XCFRAME_NUM_INSTANCES 1

/* Definitions for peripheral PMC_CFI_CFRAME_0 */
#define XPAR_PMC_CFI_CFRAME_0_COMPATIBLE "xlnx,pmc-cfi-cframe-11.0"
#define XPAR_PMC_CFI_CFRAME_0_BASEADDR 0xf12d0000
#define XPAR_PMC_CFI_CFRAME_0_HIGHADDR 0xf12d0fff

/* Canonical definitions for peripheral PMC_CFI_CFRAME_0 */
#define XPAR_XCFRAME_0_BASEADDR 0xf12d0000
#define XPAR_XCFRAME_0_HIGHADDR 0xf12d0fff
#define XPAR_XCFRAME_0_COMPATIBLE "xlnx,pmc-cfi-cframe-11.0"

#define XPAR_XCFUPMC_NUM_INSTANCES 1

/* Definitions for peripheral PMC_CFU_APB_0 */
#define XPAR_PMC_CFU_APB_0_COMPATIBLE "xlnx,pmc-cfu-apb-11.0"
#define XPAR_PMC_CFU_APB_0_BASEADDR 0xf12b0000
#define XPAR_PMC_CFU_APB_0_HIGHADDR 0xf12bffff

/* Canonical definitions for peripheral PMC_CFU_APB_0 */
#define XPAR_XCFUPMC_0_BASEADDR 0xf12b0000
#define XPAR_XCFUPMC_0_HIGHADDR 0xf12bffff
#define XPAR_XCFUPMC_0_COMPATIBLE "xlnx,pmc-cfu-apb-11.0"

#define XPAR_XCSUDMA_NUM_INSTANCES 2

/* Definitions for peripheral DMA0 */
#define XPAR_DMA0_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_DMA0_BASEADDR 0xf11c0000
#define XPAR_DMA0_HIGHADDR 0xf11cffff
#define XPAR_DMA0_DMA_TYPE 0x1
#define XPAR_DMA0_INTERRUPTS 0x40e0

/* Canonical definitions for peripheral DMA0 */
#define XPAR_XCSUDMA_0_BASEADDR 0xf11c0000
#define XPAR_XCSUDMA_0_HIGHADDR 0xf11cffff
#define XPAR_XCSUDMA_0_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_XCSUDMA_0_DMA_TYPE 0x1
#define XPAR_XCSUDMA_0_INTERRUPTS 0x40e0

/* Definitions for peripheral DMA1 */
#define XPAR_DMA1_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_DMA1_BASEADDR 0xf11d0000
#define XPAR_DMA1_HIGHADDR 0xf11dffff
#define XPAR_DMA1_DMA_TYPE 0x2
#define XPAR_DMA1_INTERRUPTS 0x40e1

/* Canonical definitions for peripheral DMA1 */
#define XPAR_XCSUDMA_1_BASEADDR 0xf11d0000
#define XPAR_XCSUDMA_1_HIGHADDR 0xf11dffff
#define XPAR_XCSUDMA_1_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_XCSUDMA_1_DMA_TYPE 0x2
#define XPAR_XCSUDMA_1_INTERRUPTS 0x40e1

#define XPAR_XEMACPS_NUM_INSTANCES 1

/* Definitions for peripheral GEM1 */
#define XPAR_GEM1_COMPATIBLE "xlnx,versal-gem"
#define XPAR_GEM1_BASEADDR 0xf1a70000
#define XPAR_GEM1_HIGHADDR 0xf1a70fff
#define XPAR_GEM1_DMA_COHERENT 0x1
#define XPAR_GEM1_INTERRUPTS 0x4029
#define XPAR_GEM1_INTERRUPTS_1 0x4029
#define XPAR_GEM1_CLOCKS 0x33
#define XPAR_GEM1_PHY_MODE "rgmii-id"
#define XPAR_GEM1_PHY_HANDLE 0x1

/* Canonical definitions for peripheral GEM1 */
#define XPAR_XEMACPS_0_BASEADDR 0xf1a70000
#define XPAR_XEMACPS_0_HIGHADDR 0xf1a70fff
#define XPAR_XEMACPS_0_COMPATIBLE "xlnx,versal-gem"
#define XPAR_XEMACPS_0_CLOCKS 0x33
#define XPAR_XEMACPS_0_DMA_COHERENT 0x1
#define XPAR_XEMACPS_0_INTERRUPTS 0x4029
#define XPAR_XEMACPS_0_PHY_MODE "rgmii-id"
#define XPAR_XEMACPS_0_PHY_HANDLE 0x1

#define XPAR_XGPIOPS_NUM_INSTANCES 2

/* Definitions for peripheral GPIO0 */
#define XPAR_GPIO0_COMPATIBLE "xlnx,versal-gpio-1.0"
#define XPAR_GPIO0_BASEADDR 0xf1a50000
#define XPAR_GPIO0_HIGHADDR 0xf1a50fff
#define XPAR_GPIO0_INTERRUPTS 0x4014

/* Canonical definitions for peripheral GPIO0 */
#define XPAR_XGPIOPS_0_BASEADDR 0xf1a50000
#define XPAR_XGPIOPS_0_HIGHADDR 0xf1a50fff
#define XPAR_XGPIOPS_0_COMPATIBLE "xlnx,versal-gpio-1.0"
#define XPAR_XGPIOPS_0_INTERRUPTS 0x4014

/* Definitions for peripheral GPIO1 */
#define XPAR_GPIO1_COMPATIBLE "xlnx,pmc-gpio-1.0"
#define XPAR_GPIO1_BASEADDR 0xf1020000
#define XPAR_GPIO1_HIGHADDR 0xf1020fff
#define XPAR_GPIO1_INTERRUPTS 0x40ca

/* Canonical definitions for peripheral GPIO1 */
#define XPAR_XGPIOPS_1_BASEADDR 0xf1020000
#define XPAR_XGPIOPS_1_HIGHADDR 0xf1020fff
#define XPAR_XGPIOPS_1_COMPATIBLE "xlnx,pmc-gpio-1.0"
#define XPAR_XGPIOPS_1_INTERRUPTS 0x40ca

#define XPAR_XIOMODULE_NUM_INSTANCES 1

/* Definitions for peripheral IOMODULE0 */
#define XPAR_IOMODULE0_COMPATIBLE "xlnx,iomodule-3.1"
#define XPAR_IOMODULE0_BASEADDR 0xf0300000
#define XPAR_IOMODULE0_HIGHADDR 0xf0300fff
#define XPAR_IOMODULE0_BASEADDR_1 0xffffffffffffffff
#define XPAR_IOMODULE0_INTC_HAS_FAST 0x0
#define XPAR_IOMODULE0_INTC_BASE_VECTORS 0xf0240000
#define XPAR_IOMODULE0_INTC_ADDR_WIDTH 0x20
#define XPAR_IOMODULE0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_IOMODULE0_OPTIONS 0x1
#define XPAR_IOMODULE0_CLOCK_FREQ 0x5f5e100
#define XPAR_IOMODULE0_UART_BAUDRATE 0x1c200
#define XPAR_IOMODULE0_PIT_USED_0 1
#define XPAR_IOMODULE0_PIT_USED_1 1
#define XPAR_IOMODULE0_PIT_USED_2 1
#define XPAR_IOMODULE0_PIT_USED_3 1
#define XPAR_IOMODULE0_PIT_SIZE_0 32
#define XPAR_IOMODULE0_PIT_SIZE_1 32
#define XPAR_IOMODULE0_PIT_SIZE_2 32
#define XPAR_IOMODULE0_PIT_SIZE_3 32
#define XPAR_IOMODULE0_PIT_MASK_0 4294967295
#define XPAR_IOMODULE0_PIT_MASK_1 4294967295
#define XPAR_IOMODULE0_PIT_MASK_2 4294967295
#define XPAR_IOMODULE0_PIT_MASK_3 4294967295
#define XPAR_IOMODULE0_PIT_PRESCALER_0 9
#define XPAR_IOMODULE0_PIT_PRESCALER_1 0
#define XPAR_IOMODULE0_PIT_PRESCALER_2 9
#define XPAR_IOMODULE0_PIT_PRESCALER_3 0
#define XPAR_IOMODULE0_PIT_READABLE_0 1
#define XPAR_IOMODULE0_PIT_READABLE_1 1
#define XPAR_IOMODULE0_PIT_READABLE_2 1
#define XPAR_IOMODULE0_PIT_READABLE_3 1
#define XPAR_IOMODULE0_GPO_INIT_0 0
#define XPAR_IOMODULE0_GPO_INIT_1 0
#define XPAR_IOMODULE0_GPO_INIT_2 0
#define XPAR_IOMODULE0_GPO_INIT_3 0
#define XPAR_IOMODULE0_MAX_INTR_SIZE 0x20
#define XPAR_IOMODULE0_INTC_INTR_SIZE 0x10
#define XPAR_IOMODULE0_INTC_USE_EXT_INTR 0x1
#define XPAR_IOMODULE0_INTC_POSITIVE 0xffff
#define XPAR_IOMODULE0_UART_PROG_BAUDRATE 0x1
#define XPAR_IOMODULE0_UART_DATA_BITS 0x8
#define XPAR_IOMODULE0_UART_USE_PARITY 0x0
#define XPAR_IOMODULE0_UART_ODD_PARITY 0x0
#define XPAR_IOMODULE0_UART_RX_INTERRUPT 0x1
#define XPAR_IOMODULE0_UART_TX_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_UART_RX 0x1
#define XPAR_IOMODULE0_USE_UART_TX 0x1
#define XPAR_IOMODULE0_UART_ERROR_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_FIT1 0x0
#define XPAR_IOMODULE0_FIT1_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT1_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_FIT2 0x0
#define XPAR_IOMODULE0_FIT2_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT2_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_FIT3 0x0
#define XPAR_IOMODULE0_FIT3_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT3_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_FIT4 0x0
#define XPAR_IOMODULE0_FIT4_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT4_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_PIT1 0x1
#define XPAR_IOMODULE0_PIT1_SIZE 0x20
#define XPAR_IOMODULE0_PIT1_READABLE 0x1
#define XPAR_IOMODULE0_PIT1_PRESCALER 0x9
#define XPAR_IOMODULE0_PIT1_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_PIT2 0x1
#define XPAR_IOMODULE0_PIT2_SIZE 0x20
#define XPAR_IOMODULE0_PIT2_READABLE 0x1
#define XPAR_IOMODULE0_PIT2_PRESCALER 0x0
#define XPAR_IOMODULE0_PIT2_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_PIT3 0x1
#define XPAR_IOMODULE0_PIT3_SIZE 0x20
#define XPAR_IOMODULE0_PIT3_READABLE 0x1
#define XPAR_IOMODULE0_PIT3_PRESCALER 0x9
#define XPAR_IOMODULE0_PIT3_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_PIT4 0x1
#define XPAR_IOMODULE0_PIT4_SIZE 0x20
#define XPAR_IOMODULE0_PIT4_READABLE 0x1
#define XPAR_IOMODULE0_PIT4_PRESCALER 0x0
#define XPAR_IOMODULE0_PIT4_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_GPO1 0x1
#define XPAR_IOMODULE0_GPO1_SIZE 0x3
#define XPAR_IOMODULE0_GPO1_INIT 0x0
#define XPAR_IOMODULE0_USE_GPO2 0x0
#define XPAR_IOMODULE0_GPO2_SIZE 0x20
#define XPAR_IOMODULE0_GPO2_INIT 0x0
#define XPAR_IOMODULE0_USE_GPO3 0x0
#define XPAR_IOMODULE0_GPO3_SIZE 0x20
#define XPAR_IOMODULE0_GPO3_INIT 0x0
#define XPAR_IOMODULE0_USE_GPO4 0x0
#define XPAR_IOMODULE0_GPO4_SIZE 0x20
#define XPAR_IOMODULE0_GPO4_INIT 0x0
#define XPAR_IOMODULE0_USE_GPI1 0x0
#define XPAR_IOMODULE0_GPI1_SIZE 0x20
#define XPAR_IOMODULE0_GPI1_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_GPI2 0x0
#define XPAR_IOMODULE0_GPI2_SIZE 0x20
#define XPAR_IOMODULE0_GPI2_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_GPI3 0x0
#define XPAR_IOMODULE0_GPI3_SIZE 0x20
#define XPAR_IOMODULE0_GPI3_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_GPI4 0x0
#define XPAR_IOMODULE0_GPI4_SIZE 0x20
#define XPAR_IOMODULE0_GPI4_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_IO_BUS 0x0
#define XPAR_IOMODULE0_IO_MASK 0xfffe0000
#define XPAR_IOMODULE0_FREQ 0x5f5e100
#define XPAR_IOMODULE0_IO_BASEADDR_0 4294967295
#define XPAR_IOMODULE0_IO_BASEADDR_1 4294967295

/* Canonical definitions for peripheral IOMODULE0 */
#define XPAR_XIOMODULE_0_BASEADDR 0xf0300000
#define XPAR_XIOMODULE_0_HIGHADDR 0xf0300fff
#define XPAR_XIOMODULE_0_COMPATIBLE "xlnx,iomodule-3.1"
#define XPAR_XIOMODULE_0_CLOCK_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_FIT1_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT1_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT2_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT2_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT3_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT3_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT4_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT4_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_GPO_INIT_0 0
#define XPAR_XIOMODULE_0_GPO_INIT_1 0
#define XPAR_XIOMODULE_0_GPO_INIT_2 0
#define XPAR_XIOMODULE_0_GPO_INIT_3 0
#define XPAR_XIOMODULE_0_GPO1_SIZE 0x3
#define XPAR_XIOMODULE_0_GPO1_INIT 0x0
#define XPAR_XIOMODULE_0_GPO2_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO2_INIT 0x0
#define XPAR_XIOMODULE_0_GPO3_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO3_INIT 0x0
#define XPAR_XIOMODULE_0_GPO4_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO4_INIT 0x0
#define XPAR_XIOMODULE_0_GPI1_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI1_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI2_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI2_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI3_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI3_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI4_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI4_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_INTC_HAS_FAST 0x0
#define XPAR_XIOMODULE_0_INTC_BASE_VECTORS 0xf0240000
#define XPAR_XIOMODULE_0_INTC_ADDR_WIDTH 0x20
#define XPAR_XIOMODULE_0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_XIOMODULE_0_INTC_INTR_SIZE 0x10
#define XPAR_XIOMODULE_0_INTC_USE_EXT_INTR 0x1
#define XPAR_XIOMODULE_0_INTC_POSITIVE 0xffff
#define XPAR_XIOMODULE_0_IO_MASK 0xfffe0000
#define XPAR_XIOMODULE_0_IO_BASEADDR_0 4294967295
#define XPAR_XIOMODULE_0_IO_BASEADDR_1 4294967295
#define XPAR_XIOMODULE_0_MAX_INTR_SIZE 0x20
#define XPAR_XIOMODULE_0_OPTIONS 0x1
#define XPAR_XIOMODULE_0_PIT_USED_0 1
#define XPAR_XIOMODULE_0_PIT_USED_1 1
#define XPAR_XIOMODULE_0_PIT_USED_2 1
#define XPAR_XIOMODULE_0_PIT_USED_3 1
#define XPAR_XIOMODULE_0_PIT_SIZE_0 32
#define XPAR_XIOMODULE_0_PIT_SIZE_1 32
#define XPAR_XIOMODULE_0_PIT_SIZE_2 32
#define XPAR_XIOMODULE_0_PIT_SIZE_3 32
#define XPAR_XIOMODULE_0_PIT_MASK_0 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_1 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_2 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_3 4294967295
#define XPAR_XIOMODULE_0_PIT_PRESCALER_0 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_1 0
#define XPAR_XIOMODULE_0_PIT_PRESCALER_2 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_3 0
#define XPAR_XIOMODULE_0_PIT_READABLE_0 1
#define XPAR_XIOMODULE_0_PIT_READABLE_1 1
#define XPAR_XIOMODULE_0_PIT_READABLE_2 1
#define XPAR_XIOMODULE_0_PIT_READABLE_3 1
#define XPAR_XIOMODULE_0_PIT1_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT1_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT1_PRESCALER 0x9
#define XPAR_XIOMODULE_0_PIT1_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT2_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT2_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT2_PRESCALER 0x0
#define XPAR_XIOMODULE_0_PIT2_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT3_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT3_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT3_PRESCALER 0x9
#define XPAR_XIOMODULE_0_PIT3_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT4_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT4_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT4_PRESCALER 0x0
#define XPAR_XIOMODULE_0_PIT4_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_UART_BAUDRATE 0x1c200
#define XPAR_XIOMODULE_0_UART_PROG_BAUDRATE 0x1
#define XPAR_XIOMODULE_0_UART_DATA_BITS 0x8
#define XPAR_XIOMODULE_0_UART_USE_PARITY 0x0
#define XPAR_XIOMODULE_0_UART_ODD_PARITY 0x0
#define XPAR_XIOMODULE_0_UART_RX_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_UART_TX_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_USE_UART_RX 0x1
#define XPAR_XIOMODULE_0_USE_UART_TX 0x1
#define XPAR_XIOMODULE_0_UART_ERROR_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_USE_FIT1 0x0
#define XPAR_XIOMODULE_0_USE_FIT2 0x0
#define XPAR_XIOMODULE_0_USE_FIT3 0x0
#define XPAR_XIOMODULE_0_USE_FIT4 0x0
#define XPAR_XIOMODULE_0_USE_PIT1 0x1
#define XPAR_XIOMODULE_0_USE_PIT2 0x1
#define XPAR_XIOMODULE_0_USE_PIT3 0x1
#define XPAR_XIOMODULE_0_USE_PIT4 0x1
#define XPAR_XIOMODULE_0_USE_GPO1 0x1
#define XPAR_XIOMODULE_0_USE_GPO2 0x0
#define XPAR_XIOMODULE_0_USE_GPO3 0x0
#define XPAR_XIOMODULE_0_USE_GPO4 0x0
#define XPAR_XIOMODULE_0_USE_GPI1 0x0
#define XPAR_XIOMODULE_0_USE_GPI2 0x0
#define XPAR_XIOMODULE_0_USE_GPI3 0x0
#define XPAR_XIOMODULE_0_USE_GPI4 0x0
#define XPAR_XIOMODULE_0_USE_IO_BUS 0x0

#define XPAR_XIPIPSU_NUM_INSTANCES 2

/* Definitions for peripheral IPI_PMC */
#define XPAR_IPI_PMC_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_IPI_PMC_BASEADDR 0xeb320000
#define XPAR_IPI_PMC_HIGHADDR 0xeb32ffff
#define XPAR_IPI_PMC_BASEADDR_1 0xeb3f0200
#define XPAR_IPI_PMC_IPI_BITMASK 0x2
#define XPAR_IPI_PMC_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PMC_INTERRUPTS 0x403b
#define XPAR_IPI_PMC_INTR 0x5b
#define XPAR_IPI_PMC_IPI_TARGET_COUNT 0x10
#define XPAR_IPI_PMC_0_IPI_BITMASK 0x1
#define XPAR_IPI_PMC_0_IPI_BUF_INDEX 0x0
#define XPAR_IPI_PMC_1_IPI_BITMASK 0x4
#define XPAR_IPI_PMC_1_IPI_BUF_INDEX 0x2
#define XPAR_IPI_PMC_2_IPI_BITMASK 0x8
#define XPAR_IPI_PMC_2_IPI_BUF_INDEX 0x3
#define XPAR_IPI_PMC_3_IPI_BITMASK 0x400
#define XPAR_IPI_PMC_3_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_4_IPI_BITMASK 0x10
#define XPAR_IPI_PMC_4_IPI_BUF_INDEX 0x4
#define XPAR_IPI_PMC_5_IPI_BITMASK 0x800
#define XPAR_IPI_PMC_5_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_6_IPI_BITMASK 0x20
#define XPAR_IPI_PMC_6_IPI_BUF_INDEX 0x5
#define XPAR_IPI_PMC_7_IPI_BITMASK 0x1000
#define XPAR_IPI_PMC_7_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_8_IPI_BITMASK 0x40
#define XPAR_IPI_PMC_8_IPI_BUF_INDEX 0x6
#define XPAR_IPI_PMC_9_IPI_BITMASK 0x2000
#define XPAR_IPI_PMC_9_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_10_IPI_BITMASK 0x80
#define XPAR_IPI_PMC_10_IPI_BUF_INDEX 0x7
#define XPAR_IPI_PMC_11_IPI_BITMASK 0x4000
#define XPAR_IPI_PMC_11_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_12_IPI_BITMASK 0x200
#define XPAR_IPI_PMC_12_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_13_IPI_BITMASK 0x8000
#define XPAR_IPI_PMC_13_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_14_IPI_BITMASK 0x2
#define XPAR_IPI_PMC_14_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PMC_15_IPI_BITMASK 0x100
#define XPAR_IPI_PMC_15_IPI_BUF_INDEX 0xffff

/* Canonical definitions for peripheral IPI_PMC */
#define XPAR_XIPIPSU_0_BASEADDR 0xeb320000
#define XPAR_XIPIPSU_0_HIGHADDR 0xeb32ffff
#define XPAR_XIPIPSU_0_INTR 0x5b
#define XPAR_XIPIPSU_0_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_XIPIPSU_0_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_0_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_0_INTERRUPTS 0x403b
#define XPAR_XIPIPSU_0_IPI_TARGET_COUNT 0x10
#define XPAR_XIPIPSU_0_CH0_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_0_CH0_IPI_BUF_INDEX 0x0
#define XPAR_XIPIPSU_0_CH1_IPI_BITMASK 0x4
#define XPAR_XIPIPSU_0_CH1_IPI_BUF_INDEX 0x2
#define XPAR_XIPIPSU_0_CH2_IPI_BITMASK 0x8
#define XPAR_XIPIPSU_0_CH2_IPI_BUF_INDEX 0x3
#define XPAR_XIPIPSU_0_CH3_IPI_BITMASK 0x400
#define XPAR_XIPIPSU_0_CH3_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH4_IPI_BITMASK 0x10
#define XPAR_XIPIPSU_0_CH4_IPI_BUF_INDEX 0x4
#define XPAR_XIPIPSU_0_CH5_IPI_BITMASK 0x800
#define XPAR_XIPIPSU_0_CH5_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH6_IPI_BITMASK 0x20
#define XPAR_XIPIPSU_0_CH6_IPI_BUF_INDEX 0x5
#define XPAR_XIPIPSU_0_CH7_IPI_BITMASK 0x1000
#define XPAR_XIPIPSU_0_CH7_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH8_IPI_BITMASK 0x40
#define XPAR_XIPIPSU_0_CH8_IPI_BUF_INDEX 0x6
#define XPAR_XIPIPSU_0_CH9_IPI_BITMASK 0x2000
#define XPAR_XIPIPSU_0_CH9_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH10_IPI_BITMASK 0x80
#define XPAR_XIPIPSU_0_CH10_IPI_BUF_INDEX 0x7
#define XPAR_XIPIPSU_0_CH11_IPI_BITMASK 0x4000
#define XPAR_XIPIPSU_0_CH11_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH12_IPI_BITMASK 0x200
#define XPAR_XIPIPSU_0_CH12_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH13_IPI_BITMASK 0x8000
#define XPAR_XIPIPSU_0_CH13_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH14_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_0_CH14_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_0_CH15_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_0_CH15_IPI_BUF_INDEX 0xffff

/* Definitions for peripheral IPI_PMC_NOBUF */
#define XPAR_IPI_PMC_NOBUF_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_IPI_PMC_NOBUF_BASEADDR 0xeb390000
#define XPAR_IPI_PMC_NOBUF_HIGHADDR 0xeb39ffff
#define XPAR_IPI_PMC_NOBUF_IPI_BITMASK 0x100
#define XPAR_IPI_PMC_NOBUF_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_INTERRUPTS 0x403c
#define XPAR_IPI_PMC_NOBUF_INTR 0x5c
#define XPAR_IPI_PMC_NOBUF_IPI_TARGET_COUNT 0x10
#define XPAR_IPI_PMC_NOBUF_0_IPI_BITMASK 0x1
#define XPAR_IPI_PMC_NOBUF_0_IPI_BUF_INDEX 0x0
#define XPAR_IPI_PMC_NOBUF_1_IPI_BITMASK 0x4
#define XPAR_IPI_PMC_NOBUF_1_IPI_BUF_INDEX 0x2
#define XPAR_IPI_PMC_NOBUF_2_IPI_BITMASK 0x8
#define XPAR_IPI_PMC_NOBUF_2_IPI_BUF_INDEX 0x3
#define XPAR_IPI_PMC_NOBUF_3_IPI_BITMASK 0x400
#define XPAR_IPI_PMC_NOBUF_3_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_4_IPI_BITMASK 0x10
#define XPAR_IPI_PMC_NOBUF_4_IPI_BUF_INDEX 0x4
#define XPAR_IPI_PMC_NOBUF_5_IPI_BITMASK 0x800
#define XPAR_IPI_PMC_NOBUF_5_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_6_IPI_BITMASK 0x20
#define XPAR_IPI_PMC_NOBUF_6_IPI_BUF_INDEX 0x5
#define XPAR_IPI_PMC_NOBUF_7_IPI_BITMASK 0x1000
#define XPAR_IPI_PMC_NOBUF_7_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_8_IPI_BITMASK 0x40
#define XPAR_IPI_PMC_NOBUF_8_IPI_BUF_INDEX 0x6
#define XPAR_IPI_PMC_NOBUF_9_IPI_BITMASK 0x2000
#define XPAR_IPI_PMC_NOBUF_9_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_10_IPI_BITMASK 0x80
#define XPAR_IPI_PMC_NOBUF_10_IPI_BUF_INDEX 0x7
#define XPAR_IPI_PMC_NOBUF_11_IPI_BITMASK 0x4000
#define XPAR_IPI_PMC_NOBUF_11_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_12_IPI_BITMASK 0x200
#define XPAR_IPI_PMC_NOBUF_12_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_13_IPI_BITMASK 0x8000
#define XPAR_IPI_PMC_NOBUF_13_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_14_IPI_BITMASK 0x2
#define XPAR_IPI_PMC_NOBUF_14_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PMC_NOBUF_15_IPI_BITMASK 0x100
#define XPAR_IPI_PMC_NOBUF_15_IPI_BUF_INDEX 0xffff

/* Canonical definitions for peripheral IPI_PMC_NOBUF */
#define XPAR_XIPIPSU_1_BASEADDR 0xeb390000
#define XPAR_XIPIPSU_1_HIGHADDR 0xeb39ffff
#define XPAR_XIPIPSU_1_INTR 0x5c
#define XPAR_XIPIPSU_1_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_XIPIPSU_1_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_1_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_INTERRUPTS 0x403c
#define XPAR_XIPIPSU_1_IPI_TARGET_COUNT 0x10
#define XPAR_XIPIPSU_1_CH0_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_1_CH0_IPI_BUF_INDEX 0x0
#define XPAR_XIPIPSU_1_CH1_IPI_BITMASK 0x4
#define XPAR_XIPIPSU_1_CH1_IPI_BUF_INDEX 0x2
#define XPAR_XIPIPSU_1_CH2_IPI_BITMASK 0x8
#define XPAR_XIPIPSU_1_CH2_IPI_BUF_INDEX 0x3
#define XPAR_XIPIPSU_1_CH3_IPI_BITMASK 0x400
#define XPAR_XIPIPSU_1_CH3_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH4_IPI_BITMASK 0x10
#define XPAR_XIPIPSU_1_CH4_IPI_BUF_INDEX 0x4
#define XPAR_XIPIPSU_1_CH5_IPI_BITMASK 0x800
#define XPAR_XIPIPSU_1_CH5_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH6_IPI_BITMASK 0x20
#define XPAR_XIPIPSU_1_CH6_IPI_BUF_INDEX 0x5
#define XPAR_XIPIPSU_1_CH7_IPI_BITMASK 0x1000
#define XPAR_XIPIPSU_1_CH7_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH8_IPI_BITMASK 0x40
#define XPAR_XIPIPSU_1_CH8_IPI_BUF_INDEX 0x6
#define XPAR_XIPIPSU_1_CH9_IPI_BITMASK 0x2000
#define XPAR_XIPIPSU_1_CH9_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH10_IPI_BITMASK 0x80
#define XPAR_XIPIPSU_1_CH10_IPI_BUF_INDEX 0x7
#define XPAR_XIPIPSU_1_CH11_IPI_BITMASK 0x4000
#define XPAR_XIPIPSU_1_CH11_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH12_IPI_BITMASK 0x200
#define XPAR_XIPIPSU_1_CH12_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH13_IPI_BITMASK 0x8000
#define XPAR_XIPIPSU_1_CH13_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH14_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_1_CH14_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_1_CH15_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_1_CH15_IPI_BUF_INDEX 0xffff

#define XPAR_XOSPIPSV_NUM_INSTANCES 1

/* Definitions for peripheral OSPI */
#define XPAR_OSPI_COMPATIBLE "amd,versal2-ospi"
#define XPAR_OSPI_BASEADDR 0xf1010000
#define XPAR_OSPI_HIGHADDR 0xf101ffff
#define XPAR_OSPI_BASEADDR_1 0xc0000000
#define XPAR_OSPI_OSPI_CLK_FREQ_HZ 0xbebba31
#define XPAR_OSPI_IS_CACHE_COHERENT 0x0
#define XPAR_OSPI_OSPI_MODE 0x0
#define XPAR_OSPI_INTERRUPTS 0x40d8
#define XPAR_OSPI_OSPI_BUS_WIDTH 0x8

/* Canonical definitions for peripheral OSPI */
#define XPAR_XOSPIPSV_0_BASEADDR 0xf1010000
#define XPAR_XOSPIPSV_0_HIGHADDR 0xf101ffff
#define XPAR_XOSPIPSV_0_COMPATIBLE "amd,versal2-ospi"
#define XPAR_XOSPIPSV_0_IS_CACHE_COHERENT 0x0
#define XPAR_XOSPIPSV_0_INTERRUPTS 0x40d8
#define XPAR_XOSPIPSV_0_OSPI_CLK_FREQ_HZ 0xbebba31
#define XPAR_XOSPIPSV_0_OSPI_MODE 0x0
#define XPAR_XOSPIPSV_0_OSPI_BUS_WIDTH 0x8

#define XPAR_XSDPS_NUM_INSTANCES 1

/* Definitions for peripheral SDHCI0 */
#define XPAR_SDHCI0_COMPATIBLE "xlnx,versal-8.9a"
#define XPAR_SDHCI0_BASEADDR 0xf1040000
#define XPAR_SDHCI0_HIGHADDR 0xf104ffff
#define XPAR_SDHCI0_SDIO_CLK_FREQ_HZ 0xbebba31
#define XPAR_SDHCI0_HAS_CD 0x0
#define XPAR_SDHCI0_HAS_WP 0x0
#define XPAR_SDHCI0_BUS_WIDTH 0x8
#define XPAR_SDHCI0_MIO_BANK 0x1
#define XPAR_SDHCI0_HAS_EMIO 0x0
#define XPAR_SDHCI0_SLOT_TYPE 0x3
#define XPAR_SDHCI0_IS_CACHE_COHERENT 0x0
#define XPAR_SDHCI0_CLOCKS 0x3b
#define XPAR_SDHCI0_CLK_50_SDR_ITAP_DLY 0x2c
#define XPAR_SDHCI0_CLK_50_SDR_OTAP_DLY 0x4
#define XPAR_SDHCI0_CLK_50_DDR_ITAP_DLY 0x36
#define XPAR_SDHCI0_CLK_50_DDR_OTAP_DLY 0x3
#define XPAR_SDHCI0_CLK_100_SDR_OTAP_DLY 0x3
#define XPAR_SDHCI0_CLK_200_SDR_OTAP_DLY 0x2

/* Canonical definitions for peripheral SDHCI0 */
#define XPAR_XSDPS_0_BASEADDR 0xf1040000
#define XPAR_XSDPS_0_HIGHADDR 0xf104ffff
#define XPAR_XSDPS_0_BUS_WIDTH 0x8
#define XPAR_XSDPS_0_COMPATIBLE "xlnx,versal-8.9a"
#define XPAR_XSDPS_0_CLOCKS 0x3b
#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0x2c
#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0x4
#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0x36
#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0x3
#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0x3
#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0x2
#define XPAR_XSDPS_0_HAS_CD 0x0
#define XPAR_XSDPS_0_HAS_WP 0x0
#define XPAR_XSDPS_0_HAS_EMIO 0x0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0x0
#define XPAR_XSDPS_0_MIO_BANK 0x1
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 0xbebba31
#define XPAR_XSDPS_0_SLOT_TYPE 0x3

#define XPAR_XSYSMONPSV_NUM_INSTANCES 1

/* Definitions for peripheral SYSMON0 */
#define XPAR_SYSMON0_COMPATIBLE "xlnx,versal-sysmon"
#define XPAR_SYSMON0_BASEADDR 0xf1270000
#define XPAR_SYSMON0_HIGHADDR 0xf1273fff

/* Canonical definitions for peripheral SYSMON0 */
#define XPAR_XSYSMONPSV_0_BASEADDR 0xf1270000
#define XPAR_XSYSMONPSV_0_HIGHADDR 0xf1273fff
#define XPAR_XSYSMONPSV_0_COMPATIBLE "xlnx,versal-sysmon"

#define XPAR_XTRNGPSX_NUM_INSTANCES 1

/* Definitions for peripheral TRNG */
#define XPAR_TRNG_COMPATIBLE "xlnx,pmc-trng-11.0"
#define XPAR_TRNG_BASEADDR 0xf1230000
#define XPAR_TRNG_HIGHADDR 0xf123ffff

/* Canonical definitions for peripheral TRNG */
#define XPAR_XTRNGPSX_0_BASEADDR 0xf1230000
#define XPAR_XTRNGPSX_0_HIGHADDR 0xf123ffff
#define XPAR_XTRNGPSX_0_COMPATIBLE "xlnx,pmc-trng-11.0"

#define XPAR_XTTCPS_NUM_INSTANCES 8

/* Definitions for peripheral TTC0 */
#define XPAR_TTC0_COMPATIBLE "cdns,ttc"
#define XPAR_TTC0_BASEADDR 0xf1e60000
#define XPAR_TTC0_HIGHADDR 0xf1e60fff
#define XPAR_TTC0_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC0_INTERRUPTS 0x402b
#define XPAR_TTC0_INTERRUPTS_1 0x402b
#define XPAR_TTC0_INTERRUPTS_2 0x402b
#define XPAR_TTC0_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC0 */
#define XPAR_XTTCPS_0_BASEADDR 0xf1e60000
#define XPAR_XTTCPS_0_HIGHADDR 0xf1e60fff
#define XPAR_XTTCPS_0_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_0_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_0_INTERRUPTS 0x402b
#define XPAR_XTTCPS_0_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC1 */
#define XPAR_TTC1_COMPATIBLE "cdns,ttc"
#define XPAR_TTC1_BASEADDR 0xf1e70000
#define XPAR_TTC1_HIGHADDR 0xf1e70fff
#define XPAR_TTC1_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC1_INTERRUPTS 0x402c
#define XPAR_TTC1_INTERRUPTS_1 0x402c
#define XPAR_TTC1_INTERRUPTS_2 0x402c
#define XPAR_TTC1_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC1 */
#define XPAR_XTTCPS_1_BASEADDR 0xf1e70000
#define XPAR_XTTCPS_1_HIGHADDR 0xf1e70fff
#define XPAR_XTTCPS_1_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_1_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_1_INTERRUPTS 0x402c
#define XPAR_XTTCPS_1_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC2 */
#define XPAR_TTC2_COMPATIBLE "cdns,ttc"
#define XPAR_TTC2_BASEADDR 0xf1e80000
#define XPAR_TTC2_HIGHADDR 0xf1e80fff
#define XPAR_TTC2_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC2_INTERRUPTS 0x402d
#define XPAR_TTC2_INTERRUPTS_1 0x402d
#define XPAR_TTC2_INTERRUPTS_2 0x402d
#define XPAR_TTC2_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC2 */
#define XPAR_XTTCPS_2_BASEADDR 0xf1e80000
#define XPAR_XTTCPS_2_HIGHADDR 0xf1e80fff
#define XPAR_XTTCPS_2_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_2_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_2_INTERRUPTS 0x402d
#define XPAR_XTTCPS_2_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC3 */
#define XPAR_TTC3_COMPATIBLE "cdns,ttc"
#define XPAR_TTC3_BASEADDR 0xf1e90000
#define XPAR_TTC3_HIGHADDR 0xf1e90fff
#define XPAR_TTC3_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC3_INTERRUPTS 0x402e
#define XPAR_TTC3_INTERRUPTS_1 0x402e
#define XPAR_TTC3_INTERRUPTS_2 0x402e
#define XPAR_TTC3_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC3 */
#define XPAR_XTTCPS_3_BASEADDR 0xf1e90000
#define XPAR_XTTCPS_3_HIGHADDR 0xf1e90fff
#define XPAR_XTTCPS_3_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_3_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_3_INTERRUPTS 0x402e
#define XPAR_XTTCPS_3_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC4 */
#define XPAR_TTC4_COMPATIBLE "cdns,ttc"
#define XPAR_TTC4_BASEADDR 0xf1ea0000
#define XPAR_TTC4_HIGHADDR 0xf1ea0fff
#define XPAR_TTC4_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC4_INTERRUPTS 0x402f
#define XPAR_TTC4_INTERRUPTS_1 0x402f
#define XPAR_TTC4_INTERRUPTS_2 0x402f
#define XPAR_TTC4_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC4 */
#define XPAR_XTTCPS_4_BASEADDR 0xf1ea0000
#define XPAR_XTTCPS_4_HIGHADDR 0xf1ea0fff
#define XPAR_XTTCPS_4_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_4_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_4_INTERRUPTS 0x402f
#define XPAR_XTTCPS_4_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC5 */
#define XPAR_TTC5_COMPATIBLE "cdns,ttc"
#define XPAR_TTC5_BASEADDR 0xf1eb0000
#define XPAR_TTC5_HIGHADDR 0xf1eb0fff
#define XPAR_TTC5_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC5_INTERRUPTS 0x4030
#define XPAR_TTC5_INTERRUPTS_1 0x4030
#define XPAR_TTC5_INTERRUPTS_2 0x4030
#define XPAR_TTC5_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC5 */
#define XPAR_XTTCPS_5_BASEADDR 0xf1eb0000
#define XPAR_XTTCPS_5_HIGHADDR 0xf1eb0fff
#define XPAR_XTTCPS_5_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_5_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_5_INTERRUPTS 0x4030
#define XPAR_XTTCPS_5_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC6 */
#define XPAR_TTC6_COMPATIBLE "cdns,ttc"
#define XPAR_TTC6_BASEADDR 0xf1ec0000
#define XPAR_TTC6_HIGHADDR 0xf1ec0fff
#define XPAR_TTC6_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC6_INTERRUPTS 0x4031
#define XPAR_TTC6_INTERRUPTS_1 0x4031
#define XPAR_TTC6_INTERRUPTS_2 0x4031
#define XPAR_TTC6_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC6 */
#define XPAR_XTTCPS_6_BASEADDR 0xf1ec0000
#define XPAR_XTTCPS_6_HIGHADDR 0xf1ec0fff
#define XPAR_XTTCPS_6_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_6_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_6_INTERRUPTS 0x4031
#define XPAR_XTTCPS_6_TTC_CLK0_CLKSRC "APB"

/* Definitions for peripheral TTC7 */
#define XPAR_TTC7_COMPATIBLE "cdns,ttc"
#define XPAR_TTC7_BASEADDR 0xf1ed0000
#define XPAR_TTC7_HIGHADDR 0xf1ed0fff
#define XPAR_TTC7_CLOCK_FREQ 0x8f0cba9
#define XPAR_TTC7_INTERRUPTS 0x4032
#define XPAR_TTC7_INTERRUPTS_1 0x4032
#define XPAR_TTC7_INTERRUPTS_2 0x4032
#define XPAR_TTC7_TTC_CLK0_CLKSRC "APB"

/* Canonical definitions for peripheral TTC7 */
#define XPAR_XTTCPS_7_BASEADDR 0xf1ed0000
#define XPAR_XTTCPS_7_HIGHADDR 0xf1ed0fff
#define XPAR_XTTCPS_7_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_7_CLOCK_FREQ 0x8f0cba9
#define XPAR_XTTCPS_7_INTERRUPTS 0x4032
#define XPAR_XTTCPS_7_TTC_CLK0_CLKSRC "APB"

#define XPAR_XUARTPSV_NUM_INSTANCES 2

/* Definitions for peripheral SERIAL0 */
#define XPAR_SERIAL0_COMPATIBLE "arm,pl011"
#define XPAR_SERIAL0_BASEADDR 0xf1920000
#define XPAR_SERIAL0_HIGHADDR 0xf1920fff
#define XPAR_SERIAL0_CLOCK_FREQ 0x5f5dd19
#define XPAR_SERIAL0_BAUDRATE 0x1c200
#define XPAR_SERIAL0_INTERRUPTS 0x4019

/* Canonical definitions for peripheral SERIAL0 */
#define XPAR_XUARTPSV_0_BASEADDR 0xf1920000
#define XPAR_XUARTPSV_0_HIGHADDR 0xf1920fff
#define XPAR_XUARTPSV_0_BAUDRATE 0x1c200
#define XPAR_XUARTPSV_0_COMPATIBLE "arm,pl011"
#define XPAR_XUARTPSV_0_CLOCK_FREQ 0x5f5dd19
#define XPAR_XUARTPSV_0_INTERRUPTS 0x4019

/* Definitions for peripheral SERIAL1 */
#define XPAR_SERIAL1_COMPATIBLE "arm,pl011"
#define XPAR_SERIAL1_BASEADDR 0xf1930000
#define XPAR_SERIAL1_HIGHADDR 0xf1930fff
#define XPAR_SERIAL1_CLOCK_FREQ 0x5f5dd19
#define XPAR_SERIAL1_BAUDRATE 0x1c200
#define XPAR_SERIAL1_INTERRUPTS 0x401a

/* Canonical definitions for peripheral SERIAL1 */
#define XPAR_XUARTPSV_1_BASEADDR 0xf1930000
#define XPAR_XUARTPSV_1_HIGHADDR 0xf1930fff
#define XPAR_XUARTPSV_1_BAUDRATE 0x1c200
#define XPAR_XUARTPSV_1_COMPATIBLE "arm,pl011"
#define XPAR_XUARTPSV_1_CLOCK_FREQ 0x5f5dd19
#define XPAR_XUARTPSV_1_INTERRUPTS 0x401a

#define XPAR_XUFSPSXC_NUM_INSTANCES 1

/* Definitions for peripheral UFSHC */
#define XPAR_UFSHC_COMPATIBLE "amd,versal2-ufs"
#define XPAR_UFSHC_BASEADDR 0xf10b0000
#define XPAR_UFSHC_HIGHADDR 0xf10b00ff
#define XPAR_UFSHC_CLK_FREQ_HZ 0x11e19751
#define XPAR_UFSHC_CFG_CLK_FREQ_HZ 0x18cba80
#define XPAR_UFSHC_REF_PAD_CLK_FREQ_HZ 0x18cba80
#define XPAR_UFSHC_IS_CACHE_COHERENT 0x0
#define XPAR_UFSHC_INTERRUPTS 0x40ea

/* Canonical definitions for peripheral UFSHC */
#define XPAR_XUFSPSXC_0_BASEADDR 0xf10b0000
#define XPAR_XUFSPSXC_0_HIGHADDR 0xf10b00ff
#define XPAR_XUFSPSXC_0_COMPATIBLE "amd,versal2-ufs"
#define XPAR_XUFSPSXC_0_CLK_FREQ_HZ 0x11e19751
#define XPAR_XUFSPSXC_0_CFG_CLK_FREQ_HZ 0x18cba80
#define XPAR_XUFSPSXC_0_IS_CACHE_COHERENT 0x0
#define XPAR_XUFSPSXC_0_INTERRUPTS 0x40ea
#define XPAR_XUFSPSXC_0_REF_PAD_CLK_FREQ_HZ 0x18cba80

#define XPAR_XUSBPSU_NUM_INSTANCES 1

/* Definitions for peripheral DWC3_0 */
#define XPAR_DWC3_0_COMPATIBLE "snps,dwc3"
#define XPAR_DWC3_0_BASEADDR 0xf1b00000
#define XPAR_DWC3_0_HIGHADDR 0xf1b0ffff
#define XPAR_DWC3_0_INTERRUPTS 0x401d
#define XPAR_DWC3_0_INTERRUPTS_1 0x401d
#define XPAR_DWC3_0_INTERRUPTS_2 0x4021
#define XPAR_DWC3_0_INTERRUPTS_3 0x4062

/* Canonical definitions for peripheral DWC3_0 */
#define XPAR_XUSBPSU_0_BASEADDR 0xf1b00000
#define XPAR_XUSBPSU_0_HIGHADDR 0xf1b0ffff
#define XPAR_XUSBPSU_0_COMPATIBLE "snps,dwc3"
#define XPAR_XUSBPSU_0_INTERRUPTS 0x401d

#define XPAR_XZDMA_NUM_INSTANCES 8

/* Definitions for peripheral ADMA0 */
#define XPAR_ADMA0_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA0_BASEADDR 0xebd00000
#define XPAR_ADMA0_HIGHADDR 0xebd00fff
#define XPAR_ADMA0_DMA_MODE 0x1
#define XPAR_ADMA0_DMA_COHERENT 0x1
#define XPAR_ADMA0_INTERRUPTS 0x4048

/* Canonical definitions for peripheral ADMA0 */
#define XPAR_XZDMA_0_BASEADDR 0xebd00000
#define XPAR_XZDMA_0_HIGHADDR 0xebd00fff
#define XPAR_XZDMA_0_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_0_DMA_MODE 0x1
#define XPAR_XZDMA_0_DMA_COHERENT 0x1
#define XPAR_XZDMA_0_INTERRUPTS 0x4048

/* Definitions for peripheral ADMA1 */
#define XPAR_ADMA1_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA1_BASEADDR 0xebd10000
#define XPAR_ADMA1_HIGHADDR 0xebd10fff
#define XPAR_ADMA1_DMA_MODE 0x1
#define XPAR_ADMA1_DMA_COHERENT 0x1
#define XPAR_ADMA1_INTERRUPTS 0x4049

/* Canonical definitions for peripheral ADMA1 */
#define XPAR_XZDMA_1_BASEADDR 0xebd10000
#define XPAR_XZDMA_1_HIGHADDR 0xebd10fff
#define XPAR_XZDMA_1_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_1_DMA_MODE 0x1
#define XPAR_XZDMA_1_DMA_COHERENT 0x1
#define XPAR_XZDMA_1_INTERRUPTS 0x4049

/* Definitions for peripheral ADMA2 */
#define XPAR_ADMA2_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA2_BASEADDR 0xebd20000
#define XPAR_ADMA2_HIGHADDR 0xebd20fff
#define XPAR_ADMA2_DMA_MODE 0x1
#define XPAR_ADMA2_DMA_COHERENT 0x1
#define XPAR_ADMA2_INTERRUPTS 0x404a

/* Canonical definitions for peripheral ADMA2 */
#define XPAR_XZDMA_2_BASEADDR 0xebd20000
#define XPAR_XZDMA_2_HIGHADDR 0xebd20fff
#define XPAR_XZDMA_2_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_2_DMA_MODE 0x1
#define XPAR_XZDMA_2_DMA_COHERENT 0x1
#define XPAR_XZDMA_2_INTERRUPTS 0x404a

/* Definitions for peripheral ADMA3 */
#define XPAR_ADMA3_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA3_BASEADDR 0xebd30000
#define XPAR_ADMA3_HIGHADDR 0xebd30fff
#define XPAR_ADMA3_DMA_MODE 0x1
#define XPAR_ADMA3_DMA_COHERENT 0x1
#define XPAR_ADMA3_INTERRUPTS 0x404b

/* Canonical definitions for peripheral ADMA3 */
#define XPAR_XZDMA_3_BASEADDR 0xebd30000
#define XPAR_XZDMA_3_HIGHADDR 0xebd30fff
#define XPAR_XZDMA_3_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_3_DMA_MODE 0x1
#define XPAR_XZDMA_3_DMA_COHERENT 0x1
#define XPAR_XZDMA_3_INTERRUPTS 0x404b

/* Definitions for peripheral ADMA4 */
#define XPAR_ADMA4_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA4_BASEADDR 0xebd40000
#define XPAR_ADMA4_HIGHADDR 0xebd40fff
#define XPAR_ADMA4_DMA_MODE 0x1
#define XPAR_ADMA4_DMA_COHERENT 0x1
#define XPAR_ADMA4_INTERRUPTS 0x404c

/* Canonical definitions for peripheral ADMA4 */
#define XPAR_XZDMA_4_BASEADDR 0xebd40000
#define XPAR_XZDMA_4_HIGHADDR 0xebd40fff
#define XPAR_XZDMA_4_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_4_DMA_MODE 0x1
#define XPAR_XZDMA_4_DMA_COHERENT 0x1
#define XPAR_XZDMA_4_INTERRUPTS 0x404c

/* Definitions for peripheral ADMA5 */
#define XPAR_ADMA5_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA5_BASEADDR 0xebd50000
#define XPAR_ADMA5_HIGHADDR 0xebd50fff
#define XPAR_ADMA5_DMA_MODE 0x1
#define XPAR_ADMA5_DMA_COHERENT 0x1
#define XPAR_ADMA5_INTERRUPTS 0x404d

/* Canonical definitions for peripheral ADMA5 */
#define XPAR_XZDMA_5_BASEADDR 0xebd50000
#define XPAR_XZDMA_5_HIGHADDR 0xebd50fff
#define XPAR_XZDMA_5_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_5_DMA_MODE 0x1
#define XPAR_XZDMA_5_DMA_COHERENT 0x1
#define XPAR_XZDMA_5_INTERRUPTS 0x404d

/* Definitions for peripheral ADMA6 */
#define XPAR_ADMA6_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA6_BASEADDR 0xebd60000
#define XPAR_ADMA6_HIGHADDR 0xebd60fff
#define XPAR_ADMA6_DMA_MODE 0x1
#define XPAR_ADMA6_DMA_COHERENT 0x1
#define XPAR_ADMA6_INTERRUPTS 0x404e

/* Canonical definitions for peripheral ADMA6 */
#define XPAR_XZDMA_6_BASEADDR 0xebd60000
#define XPAR_XZDMA_6_HIGHADDR 0xebd60fff
#define XPAR_XZDMA_6_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_6_DMA_MODE 0x1
#define XPAR_XZDMA_6_DMA_COHERENT 0x1
#define XPAR_XZDMA_6_INTERRUPTS 0x404e

/* Definitions for peripheral ADMA7 */
#define XPAR_ADMA7_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_ADMA7_BASEADDR 0xebd70000
#define XPAR_ADMA7_HIGHADDR 0xebd70fff
#define XPAR_ADMA7_DMA_MODE 0x1
#define XPAR_ADMA7_DMA_COHERENT 0x1
#define XPAR_ADMA7_INTERRUPTS 0x404f

/* Canonical definitions for peripheral ADMA7 */
#define XPAR_XZDMA_7_BASEADDR 0xebd70000
#define XPAR_XZDMA_7_HIGHADDR 0xebd70fff
#define XPAR_XZDMA_7_COMPATIBLE "amd,versal2-dma-1.0"
#define XPAR_XZDMA_7_DMA_MODE 0x1
#define XPAR_XZDMA_7_DMA_COHERENT 0x1
#define XPAR_XZDMA_7_INTERRUPTS 0x404f

/* Definitions for peripheral PMC_PPU1_MDM_0 */
#define XPAR_PMC_PPU1_MDM_0_BASEADDR 0xf0310000
#define XPAR_PMC_PPU1_MDM_0_HIGHADDR 0xf0317fff

/* Definitions for peripheral USB0 */
#define XPAR_USB0_BASEADDR 0xf1ee0000
#define XPAR_USB0_HIGHADDR 0xf1ee00ff

/* Canonical definitions for peripheral USB0 */
#define XPAR_USB_0_BASEADDR 0xf1ee0000
#define XPAR_USB_0_HIGHADDR 0xf1ee00ff


/*  CPU parameters definition */
#define XPAR_PMC_UNALIGNED_EXCEPTIONS 1
#define XPAR_PMC_FPU_EXCEPTION 0
#define XPAR_PMC_FSL_EXCEPTION 0
#define XPAR_PMC_DIV_ZERO_EXCEPTION 1
#define XPAR_PMC_ILL_OPCODE_EXCEPTION 1
#define XPAR_PMC_USE_STACK_PROTECTION 1
#define XPAR_PMC_FREQ 320000000
#define XPAR_PMC_USE_MSR_INSTR 1
#define XPAR_PMC_D_CACHE_LINE_SIZE 16
#define XPAR_PMC_DCACHE_ALWAYS_USED 0
#define XPAR_PMC_D_CACHE_SIZE 8192
#define XPAR_PMC_I_CACHE_LINE_SIZE 16
#define XPAR_PMC_I_CACHE_SIZE 8192
#define XPAR_PMC_ADDR_TAG_BITS 0
#define XPAR_PMC_ALLOW_DCACHE_WR 1
#define XPAR_PMC_ALLOW_ICACHE_WR 1
#define XPAR_PMC_AREA_OPTIMIZED 0
#define XPAR_PMC_CACHE_BYTE_SIZE 8192
#define XPAR_PMC_D_LMB 1
#define XPAR_PMC_I_LMB 1
#define XPAR_PMC_DCACHE_ADDR_TAG 0
#define XPAR_PMC_DCACHE_BYTE_SIZE 8192
#define XPAR_PMC_DCACHE_LINE_LEN 4
#define XPAR_PMC_DCACHE_USE_WRITEBACK 0
#define XPAR_PMC_DEBUG_ENABLED 1
#define XPAR_PMC_DYNAMIC_BUS_SIZING 0
#define XPAR_PMC_EDGE_IS_POSITIVE 1
#define XPAR_PMC_ENDIANNESS 1
#define XPAR_PMC_FSL_LINKS 0
#define XPAR_PMC_ICACHE_ALWAYS_USED 0
#define XPAR_PMC_ICACHE_LINE_LEN 4
#define XPAR_PMC_INTERCONNECT 2
#define XPAR_PMC_INTERRUPT_IS_EDGE 0
#define XPAR_PMC_MMU_DTLB_SIZE 4
#define XPAR_PMC_MMU_ITLB_SIZE 2
#define XPAR_PMC_MMU_TLB_ACCESS 3
#define XPAR_PMC_MMU_ZONES 16
#define XPAR_PMC_NUMBER_OF_PC_BRK 2
#define XPAR_PMC_NUMBER_OF_RD_ADDR_BRK 1
#define XPAR_PMC_NUMBER_OF_WR_ADDR_BRK 1
#define XPAR_PMC_OPCODE_0X0_ILLEGAL 1
#define XPAR_PMC_PVR 2
#define XPAR_PMC_PVR_USER2 0
#define XPAR_PMC_RESET_MSR 0
#define XPAR_PMC_SCO 0
#define XPAR_PMC_USE_BARREL 1
#define XPAR_PMC_USE_DCACHE 0
#define XPAR_PMC_USE_DIV 1
#define XPAR_PMC_USE_EXT_BRK 0
#define XPAR_PMC_USE_EXT_NM_BRK 0
#define XPAR_PMC_USE_EXTENDED_FSL_INSTR 0
#define XPAR_PMC_USE_FPU 0
#define XPAR_PMC_USE_HW_MUL 2
#define XPAR_PMC_USE_ICACHE 0
#define XPAR_PMC_USE_INTERRUPT 1
#define XPAR_PMC_USE_MMU 0
#define XPAR_PMC_USE_PCMP_INSTR 1
#define XPAR_PMC_D_CACHE_BASEADDR 0
#define XPAR_PMC_D_CACHE_HIGHADDR 1073741823
#define XPAR_PMC_I_CACHE_BASEADDR 0
#define XPAR_PMC_I_CACHE_HIGHADDR 1073741823
#define XPAR_PMC_REG 0
#define XPAR_PMC_BASE_VECTORS 4028891136
#define XPAR_PMC_FAULT_TOLERANT 1

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 320000000

#define XPAR_MICROBLAZE_DDR_RESERVE_SA 0

#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000

/* Number of SLRs */
#define NUMBER_OF_SLRS 0x1

/* Device ID */
#define XPAR_DEVICE_ID "xc2vm3654"

/* DDRMC5_I2C_MASTER */
#define DDRMC5_I2C_MASTER "PMC"

/* DDRMC5_DEBUG_ELF */
#define DDRMC5_DEBUG_ELF "false"

#endif  /* end of protection macro */